Re: [PATCH 1/2] mfd: Core support for the WM8400 AudioPlus HiFi CODEC and PMU

> +/* > + * wm8400_init - Generic initialisation > + * > + * The WM8400 can be configured as either an I2C or SPI device. Probe > + * functions for each bus set up the accessors then call into this to > + * set up the device itself. > + */ > +static int wm8400_init(struct wm8400 *wm8400, > + struct wm8400_platform_data *pdata) > +{ > + u16 reg; > + int ret, i; > + > + mutex_init(&wm8400->io_lock); > + > + wm8400->dev->driver_data = wm8400; > + > + /* Check that this is actually a WM8400 */ > + ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg); > + if (ret != 0) { > + dev_err(wm8400->dev, "Chip ID register read failed\n"); > + return -EIO; > + } > + if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) { > + dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n", > + be16_to_cpu(reg)); > + return -ENODEV; > + } > + > + /* We don't know what state the hardware is in and since this > + * is a PMIC we can't reset it safely so initialise the register > + * cache from the hardware. > + */ > + ret = wm8400->read_dev(wm8400->io_data, 0, > + ARRAY_SIZE(wm8400->reg_cache), > + wm8400->reg_cache); > + if (ret != 0) { > + dev_err(wm8400->dev, "Register cache read failed\n"); > + return -EIO; > + } > + for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) > + wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]); > + > + /* If the codec is in reset use hard coded values */ > + if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA)) > + for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) > + if (reg_data[i].is_codec) > + wm8400->reg_cache[i] = reg_data[i].default_val; > + > + ret = wm8400_read(wm8400, WM8400_ID, 1, &reg); > + if (ret != 0) { > + dev_err(wm8400->dev, "ID register read failed: %d\n", ret); > + return ret; > + } > + reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT; > + dev_info(wm8400->dev, "WM8400 revision %x\n", reg); > + > + if (pdata && pdata->platform_init) { > + ret = pdata->platform_init(wm8400->dev); > + if (ret != 0) > + dev_err(wm8400->dev, "Platform init failed: %d\n", > + ret); > + } else > + dev_warn(wm8400->dev, "No platform initialisation supplied\n"); > + > + return ret; > +} > + > +static void wm8400_release(struct wm8400 *wm8400) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++) > + if (wm8400->regulators[i].name) > + platform_device_unregister(&wm8400->regulators[i]); > +} > + > +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) > +static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest) > +{ > + struct i2c_client *i2c = io_data; > + struct i2c_msg xfer[2]; > + int ret; > + > + /* Write register */ > + xfer[0].addr = i2c->addr; > + xfer[0].flags = 0; > + xfer[0].len = 1; > + xfer[0].buf = ® > + > + /* Read data */ > + xfer[1].addr = i2c->addr; > + xfer[1].flags = I2C_M_RD; > + xfer[1].len = count * sizeof(u16); > + xfer[1].buf = (u8 *)dest; > + > + ret = i2c_transfer(i2c->adapter, xfer, 2); > + if (ret == 2) > + ret = 0; > + else if (ret >= 0) > + ret = -EIO; > + > + return ret; > +} > + > +static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src) > +{ > + struct i2c_client *i2c = io_data; > + u8 *msg; > + int ret; > + > + /* We add 1 byte for device register - ideally I2C would gather. */ > + msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL); > + if (msg == NULL) > + return -ENOMEM; > + > + msg[0] = reg; > + memcpy(&msg[1], src, count * sizeof(u16)); > + > + ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1); > + > + if (ret == (count * 2) + 1) > + ret = 0; > + else if (ret >= 0) > + ret = -EIO; > + > + kfree(msg); > + > + return ret; > +} > + > +static int wm8400_i2c_probe(struct i2c_client *i2c, > + const struct i2c_device_id *id) > +{ > + struct wm8400 *wm8400; > + int ret; > + > + wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL); > + if (wm8400 == NULL) { > + ret = -ENOMEM; > + goto err; > + } > + > + wm8400->io_data = i2c; > + wm8400->read_dev = wm8400_i2c_read; > + wm8400->write_dev = wm8400_i2c_write; > + wm8400->dev = &i2c->dev; > + i2c_set_clientdata(i2c, wm8400); > + > + ret = wm8400_init(wm8400, i2c->dev.platform_data); > + if (ret != 0) > + goto struct_err; > + > + return 0; > + > +struct_err: > + i2c_set_clientdata(i2c, NULL); > + kfree(wm8400); > +err: > + return ret; > +} > + > +static int wm8400_i2c_remove(struct i2c_client *i2c) > +{ > + struct wm8400 *wm8400 = i2c_get_clientdata(i2c); > + > + wm8400_release(wm8400); > + i2c_set_clientdata(i2c, NULL); > + kfree(wm8400); > + > + return 0; > +} > + > +static const struct i2c_device_id wm8400_i2c_id[] = { > + { "wm8400", 0 }, > + { } > +}; > +MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id); > + > +static struct i2c_driver wm8400_i2c_driver = { > + .driver = { > + .name = "WM8400", > + .owner = THIS_MODULE, > + }, > + .probe = wm8400_i2c_probe, > + .remove = wm8400_i2c_remove, > + .id_table = wm8400_i2c_id, > +}; > +#endif > + > +static int __init wm8400_module_init(void) > +{ > + int ret = -ENODEV; > + > +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) > + ret = i2c_add_driver(&wm8400_i2c_driver); > + if (ret != 0) > + pr_err("Failed to register I2C driver: %d\n", ret); > +#endif > + > + return ret; > +} > +module_init(wm8400_module_init); > + > +static void __exit wm8400_module_exit(void) > +{ > +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) > + i2c_del_driver(&wm8400_i2c_driver); > +#endif > +} > +module_exit(wm8400_module_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); > diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h > new file mode 100644 > index 0000000..ae6a882 > --- /dev/null > +++ b/include/linux/mfd/wm8400-private.h > @@ -0,0 +1,2095 @@ > +/* > + * wm8400 private definitions. > + * > + * Copyright 2008 Wolfson Microelectronics plc > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > + > +#ifndef __LINUX_MFD_WM8400_PRIV_H > +#define __LINUX_MFD_WM8400_PRIV_H > + > +#include <linux/mutex.h> > +#include <linux/platform_device.h> > + > +#define WM8400_REGISTER_COUNT 0x55 > + > +struct wm8400 { > + struct device *dev; > + > + int (*read_dev)(void *data, char reg, int count, u16 *dst); > + int (*write_dev)(void *data, char reg, int count, const u16 *src); > + > + struct mutex io_lock; > + void *io_data; > + > + u16 reg_cache[WM8400_REGISTER_COUNT]; > + > + struct platform_device regulators[6]; > +}; > + > +/* > + * Register values. > + */ > +#define WM8400_RESET_ID 0x00 > +#define WM8400_ID 0x01 > +#define WM8400_POWER_MANAGEMENT_1 0x02 > +#define WM8400_POWER_MANAGEMENT_2 0x03 > +#define WM8400_POWER_MANAGEMENT_3 0x04 > +#define WM8400_AUDIO_INTERFACE_1 0x05 > +#define WM8400_AUDIO_INTERFACE_2 0x06 > +#define WM8400_CLOCKING_1 0x07 > +#define WM8400_CLOCKING_2 0x08 > +#define WM8400_AUDIO_INTERFACE_3 0x09 > +#define WM8400_AUDIO_INTERFACE_4 0x0A > +#define WM8400_DAC_CTRL 0x0B > +#define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C > +#define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D > +#define WM8400_DIGITAL_SIDE_TONE 0x0E > +#define WM8400_ADC_CTRL 0x0F > +#define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10 > +#define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11 > +#define WM8400_GPIO_CTRL_1 0x12 > +#define WM8400_GPIO1_GPIO2 0x13 > +#define WM8400_GPIO3_GPIO4 0x14 > +#define WM8400_GPIO5_GPIO6 0x15 > +#define WM8400_GPIOCTRL_2 0x16 > +#define WM8400_GPIO_POL 0x17 > +#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18 > +#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19 > +#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A > +#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B > +#define WM8400_LEFT_OUTPUT_VOLUME 0x1C > +#define WM8400_RIGHT_OUTPUT_VOLUME 0x1D > +#define WM8400_LINE_OUTPUTS_VOLUME 0x1E > +#define WM8400_OUT3_4_VOLUME 0x1F > +#define WM8400_LEFT_OPGA_VOLUME 0x20 > +#define WM8400_RIGHT_OPGA_VOLUME 0x21 > +#define WM8400_SPEAKER_VOLUME 0x22 > +#define WM8400_CLASSD1 0x23 > +#define WM8400_CLASSD3 0x25 > +#define WM8400_INPUT_MIXER1 0x27 > +#define WM8400_INPUT_MIXER2 0x28 > +#define WM8400_INPUT_MIXER3 0x29 > +#define WM8400_INPUT_MIXER4 0x2A > +#define WM8400_INPUT_MIXER5 0x2B > +#define WM8400_INPUT_MIXER6 0x2C > +#define WM8400_OUTPUT_MIXER1 0x2D > +#define WM8400_OUTPUT_MIXER2 0x2E > +#define WM8400_OUTPUT_MIXER3 0x2F > +#define WM8400_OUTPUT_MIXER4 0x30 > +#define WM8400_OUTPUT_MIXER5 0x31 > +#define WM8400_OUTPUT_MIXER6 0x32 > +#define WM8400_OUT3_4_MIXER 0x33 > +#define WM8400_LINE_MIXER1 0x34 > +#define WM8400_LINE_MIXER2 0x35 > +#define WM8400_SPEAKER_MIXER 0x36 > +#define WM8400_ADDITIONAL_CONTROL 0x37 > +#define WM8400_ANTIPOP1 0x38 > +#define WM8400_ANTIPOP2 0x39 > +#define WM8400_MICBIAS 0x3A > +#define WM8400_FLL_CONTROL_1 0x3C > +#define WM8400_FLL_CONTROL_2 0x3D > +#define WM8400_FLL_CONTROL_3 0x3E > +#define WM8400_FLL_CONTROL_4 0x3F > +#define WM8400_LDO1_CONTROL 0x41 > +#define WM8400_LDO2_CONTROL 0x42 > +#define WM8400_LDO3_CONTROL 0x43 > +#define WM8400_LDO4_CONTROL 0x44 > +#define WM8400_DCDC1_CONTROL_1 0x46 > +#define WM8400_DCDC1_CONTROL_2 0x47 > +#define WM8400_DCDC2_CONTROL_1 0x48 > +#define WM8400_DCDC2_CONTROL_2 0x49 > +#define WM8400_INTERFACE 0x4B > +#define WM8400_PM_GENERAL 0x4C > +#define WM8400_PM_SHUTDOWN_CONTROL 0x4E > +#define WM8400_INTERRUPT_STATUS_1 0x4F > +#define WM8400_INTERRUPT_STATUS_1_MASK 0x50 > +#define WM8400_INTERRUPT_LEVELS 0x51 > +#define WM8400_SHUTDOWN_REASON 0x52 > +#define WM8400_LINE_CIRCUITS 0x54 > + > +/* > + * Field Definitions. > + */ > + > +/* > + * R0 (0x00) - Reset/ID > + */ > +#define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */ > +#define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */ > +#define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */ > + > +/* > + * R1 (0x01) - ID > + */ > +#define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */ > +#define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */ > +#define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */ > + > +/* > + * R2 (0x02) - Power Management (1) > + */ > +#define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */ > +#define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */ > +#define WM8400_CODEC_ENA_SHIFT 15 /* CODEC_ENA */ > +#define WM8400_CODEC_ENA_WIDTH 1 /* CODEC_ENA */ > +#define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */ > +#define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */ > +#define WM8400_SYSCLK_ENA_SHIFT 14 /* SYSCLK_ENA */ > +#define WM8400_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ > +#define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */ > +#define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */ > +#define WM8400_SPK_MIX_ENA_SHIFT 13 /* SPK_MIX_ENA */ > +#define WM8400_SPK_MIX_ENA_WIDTH 1 /* SPK_MIX_ENA */ > +#define WM8400_SPK_ENA 0x1000 /* SPK_ENA */ > +#define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */ > +#define WM8400_SPK_ENA_SHIFT 12 /* SPK_ENA */ > +#define WM8400_SPK_ENA_WIDTH 1 /* SPK_ENA */ > +#define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */ > +#define WM8400_OUT3_ENA_MASK 0x0800 /* OUT3_ENA */ > +#define WM8400_OUT3_ENA_SHIFT 11 /* OUT3_ENA */ > +#define WM8400_OUT3_ENA_WIDTH 1 /* OUT3_ENA */ > +#define WM8400_OUT4_ENA 0x0400 /* OUT4_ENA */ > +#define WM8400_OUT4_ENA_MASK 0x0400 /* OUT4_ENA */ > +#define WM8400_OUT4_ENA_SHIFT 10 /* OUT4_ENA */ > +#define WM8400_OUT4_ENA_WIDTH 1 /* OUT4_ENA */ > +#define WM8400_LOUT_ENA 0x0200 /* LOUT_ENA */ > +#define WM8400_LOUT_ENA_MASK 0x0200 /* LOUT_ENA */ > +#define WM8400_LOUT_ENA_SHIFT 9 /* LOUT_ENA */ > +#define WM8400_LOUT_ENA_WIDTH 1 /* LOUT_ENA */ > +#define WM8400_ROUT_ENA 0x0100 /* ROUT_ENA */ > +#define WM8400_ROUT_ENA_MASK 0x0100 /* ROUT_ENA */ > +#define WM8400_ROUT_ENA_SHIFT 8 /* ROUT_ENA */ > +#define WM8400_ROUT_ENA_WIDTH 1 /* ROUT_ENA */ > +#define WM8400_MIC1BIAS_ENA 0x0010 /* MIC1BIAS_ENA */ > +#define WM8400_MIC1BIAS_ENA_MASK 0x0010 /* MIC1BIAS_ENA */ > +#define WM8400_MIC1BIAS_ENA_SHIFT 4 /* MIC1BIAS_ENA */ > +#define WM8400_MIC1BIAS_ENA_WIDTH 1 /* MIC1BIAS_ENA */ > +#define WM8400_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */ > +#define WM8400_VMID_MODE_SHIFT 1 /* VMID_MODE - [2:1] */ > +#define WM8400_VMID_MODE_WIDTH 2 /* VMID_MODE - [2:1] */ > +#define WM8400_VREF_ENA 0x0001 /* VREF_ENA */ > +#define WM8400_VREF_ENA_MASK 0x0001 /* VREF_ENA */ > +#define WM8400_VREF_ENA_SHIFT 0 /* VREF_ENA */ > +#define WM8400_VREF_ENA_WIDTH 1 /* VREF_ENA */ > + > +/* > + * R3 (0x03) - Power Management (2) > + */ > +#define WM8400_FLL_ENA 0x8000 /* FLL_ENA */ > +#define WM8400_FLL_ENA_MASK 0x8000 /* FLL_ENA */ > +#define WM8400_FLL_ENA_SHIFT 15 /* FLL_ENA */ > +#define WM8400_FLL_ENA_WIDTH 1 /* FLL_ENA */ > +#define WM8400_TSHUT_ENA 0x4000 /* TSHUT_ENA */ > +#define WM8400_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */ > +#define WM8400_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */ > +#define WM8400_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ > +#define WM8400_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ > +#define WM8400_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */ > +#define WM8400_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */ > +#define WM8400_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */ > +#define WM8400_OPCLK_ENA 0x0800 /* OPCLK_ENA */ > +#define WM8400_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ > +#define WM8400_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ > +#define WM8400_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ > +#define WM8400_AINL_ENA 0x0200 /* AINL_ENA */ > +#define WM8400_AINL_ENA_MASK 0x0200 /* AINL_ENA */ > +#define WM8400_AINL_ENA_SHIFT 9 /* AINL_ENA */ > +#define WM8400_AINL_ENA_WIDTH 1 /* AINL_ENA */ > +#define WM8400_AINR_ENA 0x0100 /* AINR_ENA */ > +#define WM8400_AINR_ENA_MASK 0x0100 /* AINR_ENA */ > +#define WM8400_AINR_ENA_SHIFT 8 /* AINR_ENA */ > +#define WM8400_AINR_ENA_WIDTH 1 /* AINR_ENA */ > +#define WM8400_LIN34_ENA 0x0080 /* LIN34_ENA */ > +#define WM8400_LIN34_ENA_MASK 0x0080 /* LIN34_ENA */ > +#define WM8400_LIN34_ENA_SHIFT 7 /* LIN34_ENA */ > +#define WM8400_LIN34_ENA_WIDTH 1 /* LIN34_ENA */ > +#define WM8400_LIN12_ENA 0x0040 /* LIN12_ENA */ > +#define WM8400_LIN12_ENA_MASK 0x0040 /* LIN12_ENA */ > +#define WM8400_LIN12_ENA_SHIFT 6 /* LIN12_ENA */ > +#define WM8400_LIN12_ENA_WIDTH 1 /* LIN12_ENA */ > +#define WM8400_RIN34_ENA 0x0020 /* RIN34_ENA */ > +#define WM8400_RIN34_ENA_MASK 0x0020 /* RIN34_ENA */ > +#define WM8400_RIN34_ENA_SHIFT 5 /* RIN34_ENA */ > +#define WM8400_RIN34_ENA_WIDTH 1 /* RIN34_ENA */ > +#define WM8400_RIN12_ENA 0x0010 /* RIN12_ENA */ > +#define WM8400_RIN12_ENA_MASK 0x0010 /* RIN12_ENA */ > +#define WM8400_RIN12_ENA_SHIFT 4 /* RIN12_ENA */ > +#define WM8400_RIN12_ENA_WIDTH 1 /* RIN12_ENA */ > +#define WM8400_ADCL_ENA 0x0002 /* ADCL_ENA */ > +#define WM8400_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ > +#define WM8400_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ > +#define WM8400_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ > +#define WM8400_ADCR_ENA 0x0001 /* ADCR_ENA */ > +#define WM8400_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ > +#define WM8400_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ > +#define WM8400_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ > + > +/* > + * R4 (0x04) - Power Management (3) > + */ > +#define WM8400_LON_ENA 0x2000 /* LON_ENA */ > +#define WM8400_LON_ENA_MASK 0x2000 /* LON_ENA */ > +#define WM8400_LON_ENA_SHIFT 13 /* LON_ENA */ > +#define WM8400_LON_ENA_WIDTH 1 /* LON_ENA */ > +#define WM8400_LOP_ENA 0x1000 /* LOP_ENA */ > +#define WM8400_LOP_ENA_MASK 0x1000 /* LOP_ENA */ > +#define WM8400_LOP_ENA_SHIFT 12 /* LOP_ENA */ > +#define WM8400_LOP_ENA_WIDTH 1 /* LOP_ENA */ > +#define WM8400_RON_ENA 0x0800 /* RON_ENA */ > +#define WM8400_RON_ENA_MASK 0x0800 /* RON_ENA */ > +#define WM8400_RON_ENA_SHIFT 11 /* RON_ENA */ > +#define WM8400_RON_ENA_WIDTH 1 /* RON_ENA */ > +#define WM8400_ROP_ENA 0x0400 /* ROP_ENA */ > +#define WM8400_ROP_ENA_MASK 0x0400 /* ROP_ENA */ > +#define WM8400_ROP_ENA_SHIFT 10 /* ROP_ENA */ > +#define WM8400_ROP_ENA_WIDTH 1 /* ROP_ENA */ > +#define WM8400_LOPGA_ENA 0x0080 /* LOPGA_ENA */ > +#define WM8400_LOPGA_ENA_MASK 0x0080 /* LOPGA_ENA */ > +#define WM8400_LOPGA_ENA_SHIFT 7 /* LOPGA_ENA */ > +#define WM8400_LOPGA_ENA_WIDTH 1 /* LOPGA_ENA */ > +#define WM8400_ROPGA_ENA 0x0040 /* ROPGA_ENA */ > +#define WM8400_ROPGA_ENA_MASK 0x0040 /* ROPGA_ENA */ > +#define WM8400_ROPGA_ENA_SHIFT 6 /* ROPGA_ENA */ > +#define WM8400_ROPGA_ENA_WIDTH 1 /* ROPGA_ENA */ > +#define WM8400_LOMIX_ENA 0x0020 /* LOMIX_ENA */ > +#define WM8400_LOMIX_ENA_MASK 0x0020 /* LOMIX_ENA */ > +#define WM8400_LOMIX_ENA_SHIFT 5 /* LOMIX_ENA */ > +#define WM8400_LOMIX_ENA_WIDTH 1 /* LOMIX_ENA */ > +#define WM8400_ROMIX_ENA 0x0010 /* ROMIX_ENA */ > +#define WM8400_ROMIX_ENA_MASK 0x0010 /* ROMIX_ENA */ > +#define WM8400_ROMIX_ENA_SHIFT 4 /* ROMIX_ENA */ > +#define WM8400_ROMIX_ENA_WIDTH 1 /* ROMIX_ENA */ > +#define WM8400_DACL_ENA 0x0002 /* DACL_ENA */ > +#define WM8400_DACL_ENA_MASK 0x0002 /* DACL_ENA */ > +#define WM8400_DACL_ENA_SHIFT 1 /* DACL_ENA */ > +#define WM8400_DACL_ENA_WIDTH 1 /* DACL_ENA */ > +#define WM8400_DACR_ENA 0x0001 /* DACR_ENA */ > +#define WM8400_DACR_ENA_MASK 0x0001 /* DACR_ENA */ > +#define WM8400_DACR_ENA_SHIFT 0 /* DACR_ENA */ > +#define WM8400_DACR_ENA_WIDTH 1 /* DACR_ENA */ > + > +/* > + * R5 (0x05) - Audio Interface (1) > + */ > +#define WM8400_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */ > +#define WM8400_AIFADCL_SRC_MASK 0x8000 /* AIFADCL_SRC */ > +#define WM8400_AIFADCL_SRC_SHIFT 15 /* AIFADCL_SRC */ > +#define WM8400_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ > +#define WM8400_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */ > +#define WM8400_AIFADCR_SRC_MASK 0x4000 /* AIFADCR_SRC */ > +#define WM8400_AIFADCR_SRC_SHIFT 14 /* AIFADCR_SRC */ > +#define WM8400_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ > +#define WM8400_AIFADC_TDM 0x2000 /* AIFADC_TDM */ > +#define WM8400_AIFADC_TDM_MASK 0x2000 /* AIFADC_TDM */ > +#define WM8400_AIFADC_TDM_SHIFT 13 /* AIFADC_TDM */ > +#define WM8400_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ > +#define WM8400_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */ > +#define WM8400_AIFADC_TDM_CHAN_MASK 0x1000 /* AIFADC_TDM_CHAN */ > +#define WM8400_AIFADC_TDM_CHAN_SHIFT 12 /* AIFADC_TDM_CHAN */ > +#define WM8400_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ > +#define WM8400_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */ > +#define WM8400_AIF_BCLK_INV_MASK 0x0100 /* AIF_BCLK_INV */ > +#define WM8400_AIF_BCLK_INV_SHIFT 8 /* AIF_BCLK_INV */ > +#define WM8400_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ > +#define WM8400_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */ > +#define WM8400_AIF_LRCLK_INV_MASK 0x0080 /* AIF_LRCLK_INV */ > +#define WM8400_AIF_LRCLK_INV_SHIFT 7 /* AIF_LRCLK_INV */ > +#define WM8400_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ > +#define WM8400_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */ > +#define WM8400_AIF_WL_SHIFT 5 /* AIF_WL - [6:5] */ > +#define WM8400_AIF_WL_WIDTH 2 /* AIF_WL - [6:5] */ > +#define WM8400_AIF_WL_16BITS (0 << 5) > +#define WM8400_AIF_WL_20BITS (1 << 5) > +#define WM8400_AIF_WL_24BITS (2 << 5) > +#define WM8400_AIF_WL_32BITS (3 << 5) > +#define WM8400_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */ > +#define WM8400_AIF_FMT_SHIFT 3 /* AIF_FMT - [4:3] */ > +#define WM8400_AIF_FMT_WIDTH 2 /* AIF_FMT - [4:3] */ > +#define WM8400_AIF_FMT_RIGHTJ (0 << 3) > +#define WM8400_AIF_FMT_LEFTJ (1 << 3) > +#define WM8400_AIF_FMT_I2S (2 << 3) > +#define WM8400_AIF_FMT_DSP (3 << 3) > + > +/* > + * R6 (0x06) - Audio Interface (2) > + */ > +#define WM8400_DACL_SRC 0x8000 /* DACL_SRC */ > +#define WM8400_DACL_SRC_MASK 0x8000 /* DACL_SRC */ > +#define WM8400_DACL_SRC_SHIFT 15 /* DACL_SRC */ > +#define WM8400_DACL_SRC_WIDTH 1 /* DACL_SRC */ > +#define WM8400_DACR_SRC 0x4000 /* DACR_SRC */ > +#define WM8400_DACR_SRC_MASK 0x4000 /* DACR_SRC */ > +#define WM8400_DACR_SRC_SHIFT 14 /* DACR_SRC */ > +#define WM8400_DACR_SRC_WIDTH 1 /* DACR_SRC */ > +#define WM8400_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ > +#define WM8400_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ > +#define WM8400_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ > +#define WM8400_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ > +#define WM8400_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ > +#define WM8400_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ > +#define WM8400_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ > +#define WM8400_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ > +#define WM8400_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */ > +#define WM8400_DAC_BOOST_SHIFT 10 /* DAC_BOOST - [11:10] */ > +#define WM8400_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [11:10] */ > +#define WM8400_DAC_COMP 0x0010 /* DAC_COMP */ > +#define WM8400_DAC_COMP_MASK 0x0010 /* DAC_COMP */ > +#define WM8400_DAC_COMP_SHIFT 4 /* DAC_COMP */ > +#define WM8400_DAC_COMP_WIDTH 1 /* DAC_COMP */ > +#define WM8400_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ > +#define WM8400_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */ > +#define WM8400_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */ > +#define WM8400_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ > +#define WM8400_ADC_COMP 0x0004 /* ADC_COMP */ > +#define WM8400_ADC_COMP_MASK 0x0004 /* ADC_COMP */ > +#define WM8400_ADC_COMP_SHIFT 2 /* ADC_COMP */ > +#define WM8400_ADC_COMP_WIDTH 1 /* ADC_COMP */ > +#define WM8400_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ > +#define WM8400_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */ > +#define WM8400_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */ > +#define WM8400_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ > +#define WM8400_LOOPBACK 0x0001 /* LOOPBACK */ > +#define WM8400_LOOPBACK_MASK 0x0001 /* LOOPBACK */ > +#define WM8400_LOOPBACK_SHIFT 0 /* LOOPBACK */ > +#define WM8400_LOOPBACK_WIDTH 1 /* LOOPBACK */ > + > +/* > + * R7 (0x07) - Clocking (1) > + */ > +#define WM8400_TOCLK_RATE 0x8000 /* TOCLK_RATE */ > +#define WM8400_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */ > +#define WM8400_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */ > +#define WM8400_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */ > +#define WM8400_TOCLK_ENA 0x4000 /* TOCLK_ENA */ > +#define WM8400_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */ > +#define WM8400_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */ > +#define WM8400_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ > +#define WM8400_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */ > +#define WM8400_OPCLKDIV_SHIFT 9 /* OPCLKDIV - [12:9] */ > +#define WM8400_OPCLKDIV_WIDTH 4 /* OPCLKDIV - [12:9] */ > +#define WM8400_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ > +#define WM8400_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */ > +#define WM8400_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */ > +#define WM8400_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */ > +#define WM8400_BCLK_DIV_SHIFT 1 /* BCLK_DIV - [4:1] */ > +#define WM8400_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [4:1] */ > + > +/* > + * R8 (0x08) - Clocking (2) > + */ > +#define WM8400_MCLK_SRC 0x8000 /* MCLK_SRC */ > +#define WM8400_MCLK_SRC_MASK 0x8000 /* MCLK_SRC */ > +#define WM8400_MCLK_SRC_SHIFT 15 /* MCLK_SRC */ > +#define WM8400_MCLK_SRC_WIDTH 1 /* MCLK_SRC */ > +#define WM8400_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ > +#define WM8400_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */ > +#define WM8400_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */ > +#define WM8400_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ > +#define WM8400_CLK_FORCE 0x2000 /* CLK_FORCE */ > +#define WM8400_CLK_FORCE_MASK 0x2000 /* CLK_FORCE */ > +#define WM8400_CLK_FORCE_SHIFT 13 /* CLK_FORCE */ > +#define WM8400_CLK_FORCE_WIDTH 1 /* CLK_FORCE */ > +#define WM8400_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */ > +#define WM8400_MCLK_DIV_SHIFT 11 /* MCLK_DIV - [12:11] */ > +#define WM8400_MCLK_DIV_WIDTH 2 /* MCLK_DIV - [12:11] */ > +#define WM8400_MCLK_INV 0x0400 /* MCLK_INV */ > +#define WM8400_MCLK_INV_MASK 0x0400 /* MCLK_INV */ > +#define WM8400_MCLK_INV_SHIFT 10 /* MCLK_INV */ > +#define WM8400_MCLK_INV_WIDTH 1 /* MCLK_INV */ > +#define WM8400_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */ > +#define WM8400_ADC_CLKDIV_SHIFT 5 /* ADC_CLKDIV - [7:5] */ > +#define WM8400_ADC_CLKDIV_WIDTH 3 /* ADC_CLKDIV - [7:5] */ > +#define WM8400_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */ > +#define WM8400_DAC_CLKDIV_SHIFT 2 /* DAC_CLKDIV - [4:2] */ > +#define WM8400_DAC_CLKDIV_WIDTH 3 /* DAC_CLKDIV - [4:2] */ > + > +/* > + * R9 (0x09) - Audio Interface (3) > + */ > +#define WM8400_AIF_MSTR1 0x8000 /* AIF_MSTR1 */ > +#define WM8400_AIF_MSTR1_MASK 0x8000 /* AIF_MSTR1 */ > +#define WM8400_AIF_MSTR1_SHIFT 15 /* AIF_MSTR1 */ > +#define WM8400_AIF_MSTR1_WIDTH 1 /* AIF_MSTR1 */ > +#define WM8400_AIF_MSTR2 0x4000 /* AIF_MSTR2 */ > +#define WM8400_AIF_MSTR2_MASK 0x4000 /* AIF_MSTR2 */ > +#define WM8400_AIF_MSTR2_SHIFT 14 /* AIF_MSTR2 */ > +#define WM8400_AIF_MSTR2_WIDTH 1 /* AIF_MSTR2 */ > +#define WM8400_AIF_SEL 0x2000 /* AIF_SEL */ > +#define WM8400_AIF_SEL_MASK 0x2000 /* AIF_SEL */ > +#define WM8400_AIF_SEL_SHIFT 13 /* AIF_SEL */ > +#define WM8400_AIF_SEL_WIDTH 1 /* AIF_SEL */ > +#define WM8400_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */ > +#define WM8400_ADCLRC_DIR_MASK 0x0800 /* ADCLRC_DIR */ > +#define WM8400_ADCLRC_DIR_SHIFT 11 /* ADCLRC_DIR */ > +#define WM8400_ADCLRC_DIR_WIDTH 1 /* ADCLRC_DIR */ > +#define WM8400_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */ > +#define WM8400_ADCLRC_RATE_SHIFT 0 /* ADCLRC_RATE - [10:0] */ > +#define WM8400_ADCLRC_RATE_WIDTH 11 /* ADCLRC_RATE - [10:0] */ > + > +/* > + * R10 (0x0A) - Audio Interface (4) > + */ > +#define WM8400_ALRCGPIO1 0x8000 /* ALRCGPIO1 */ > +#define WM8400_ALRCGPIO1_MASK 0x8000 /* ALRCGPIO1 */ > +#define WM8400_ALRCGPIO1_SHIFT 15 /* ALRCGPIO1 */ > +#define WM8400_ALRCGPIO1_WIDTH 1 /* ALRCGPIO1 */ > +#define WM8400_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */ > +#define WM8400_ALRCBGPIO6_MASK 0x4000 /* ALRCBGPIO6 */ > +#define WM8400_ALRCBGPIO6_SHIFT 14 /* ALRCBGPIO6 */ > +#define WM8400_ALRCBGPIO6_WIDTH 1 /* ALRCBGPIO6 */ > +#define WM8400_AIF_TRIS 0x2000 /* AIF_TRIS */ > +#define WM8400_AIF_TRIS_MASK 0x2000 /* AIF_TRIS */ > +#define WM8400_AIF_TRIS_SHIFT 13 /* AIF_TRIS */ > +#define WM8400_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ > +#define WM8400_DACLRC_DIR 0x0800 /* DACLRC_DIR */ > +#define WM8400_DACLRC_DIR_MASK 0x0800 /* DACLRC_DIR */ > +#define WM8400_DACLRC_DIR_SHIFT 11 /* DACLRC_DIR */ > +#define WM8400_DACLRC_DIR_WIDTH 1 /* DACLRC_DIR */ > +#define WM8400_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */ > +#define WM8400_DACLRC_RATE_SHIFT 0 /* DACLRC_RATE - [10:0] */ > +#define WM8400_DACLRC_RATE_WIDTH 11 /* DACLRC_RATE - [10:0] */ > + > +/* > + * R11 (0x0B) - DAC CTRL > + */ > +#define WM8400_DAC_SDMCLK_RATE 0x2000 /* DAC_SDMCLK_RATE */ > +#define WM8400_DAC_SDMCLK_RATE_MASK 0x2000 /* DAC_SDMCLK_RATE */ > +#define WM8400_DAC_SDMCLK_RATE_SHIFT 13 /* DAC_SDMCLK_RATE */ > +#define WM8400_DAC_SDMCLK_RATE_WIDTH 1 /* DAC_SDMCLK_RATE */ > +#define WM8400_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */ > +#define WM8400_AIF_LRCLKRATE_MASK 0x0400 /* AIF_LRCLKRATE */ > +#define WM8400_AIF_LRCLKRATE_SHIFT 10 /* AIF_LRCLKRATE */ > +#define WM8400_AIF_LRCLKRATE_WIDTH 1 /* AIF_LRCLKRATE */ > +#define WM8400_DAC_MONO 0x0200 /* DAC_MONO */ > +#define WM8400_DAC_MONO_MASK 0x0200 /* DAC_MONO */ > +#define WM8400_DAC_MONO_SHIFT 9 /* DAC_MONO */ > +#define WM8400_DAC_MONO_WIDTH 1 /* DAC_MONO */ > +#define WM8400_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */ > +#define WM8400_DAC_SB_FILT_MASK 0x0100 /* DAC_SB_FILT */ > +#define WM8400_DAC_SB_FILT_SHIFT 8 /* DAC_SB_FILT */ > +#define WM8400_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ > +#define WM8400_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */ > +#define WM8400_DAC_MUTERATE_MASK 0x0080 /* DAC_MUTERATE */ > +#define WM8400_DAC_MUTERATE_SHIFT 7 /* DAC_MUTERATE */ > +#define WM8400_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ > +#define WM8400_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */ > +#define WM8400_DAC_MUTEMODE_MASK 0x0040 /* DAC_MUTEMODE */ > +#define WM8400_DAC_MUTEMODE_SHIFT 6 /* DAC_MUTEMODE */ > +#define WM8400_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ > +#define WM8400_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */ > +#define WM8400_DEEMP_SHIFT 4 /* DEEMP - [5:4] */ > +#define WM8400_DEEMP_WIDTH 2 /* DEEMP - [5:4] */ > +#define WM8400_DAC_MUTE 0x0004 /* DAC_MUTE */ > +#define WM8400_DAC_MUTE_MASK 0x0004 /* DAC_MUTE */ > +#define WM8400_DAC_MUTE_SHIFT 2 /* DAC_MUTE */ > +#define WM8400_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ > +#define WM8400_DACL_DATINV 0x0002 /* DACL_DATINV */ > +#define WM8400_DACL_DATINV_MASK 0x0002 /* DACL_DATINV */ > +#define WM8400_DACL_DATINV_SHIFT 1 /* DACL_DATINV */ > +#define WM8400_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ > +#define WM8400_DACR_DATINV 0x0001 /* DACR_DATINV */ > +#define WM8400_DACR_DATINV_MASK 0x0001 /* DACR_DATINV */ > +#define WM8400_DACR_DATINV_SHIFT 0 /* DACR_DATINV */ > +#define WM8400_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ > + > +/* > + * R12 (0x0C) - Left DAC Digital Volume > + */ > +#define WM8400_DAC_VU 0x0100 /* DAC_VU */ > +#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */ > +#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */ > +#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */ > +#define WM8400_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ > +#define WM8400_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ > +#define WM8400_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ > + > +/* > + * R13 (0x0D) - Right DAC Digital Volume > + */ > +#define WM8400_DAC_VU 0x0100 /* DAC_VU */ > +#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */ > +#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */ > +#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */ > +#define WM8400_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ > +#define WM8400_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ > +#define WM8400_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ > + > +/* > + * R14 (0x0E) - Digital Side Tone > + */ > +#define WM8400_ADCL_DAC_SVOL_MASK 0x1E00 /* ADCL_DAC_SVOL - [12:9] */ > +#define WM8400_ADCL_DAC_SVOL_SHIFT 9 /* ADCL_DAC_SVOL - [12:9] */ > +#define WM8400_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [12:9] */ > +#define WM8400_ADCR_DAC_SVOL_MASK 0x01E0 /* ADCR_DAC_SVOL - [8:5] */ > +#define WM8400_ADCR_DAC_SVOL_SHIFT 5 /* ADCR_DAC_SVOL - [8:5] */ > +#define WM8400_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [8:5] */ > +#define WM8400_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ > +#define WM8400_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ > +#define WM8400_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ > +#define WM8400_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ > +#define WM8400_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ > +#define WM8400_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ > + > +/* > + * R15 (0x0F) - ADC CTRL > + */ > +#define WM8400_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */ > +#define WM8400_ADC_HPF_ENA_MASK 0x0100 /* ADC_HPF_ENA */ > +#define WM8400_ADC_HPF_ENA_SHIFT 8 /* ADC_HPF_ENA */ > +#define WM8400_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */ > +#define WM8400_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ > +#define WM8400_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ > +#define WM8400_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ > +#define WM8400_ADCL_DATINV 0x0002 /* ADCL_DATINV */ > +#define WM8400_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ > +#define WM8400_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ > +#define WM8400_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ > +#define WM8400_ADCR_DATINV 0x0001 /* ADCR_DATINV */ > +#define WM8400_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ > +#define WM8400_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ > +#define WM8400_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ > + > +/* > + * R16 (0x10) - Left ADC Digital Volume > + */ > +#define WM8400_ADC_VU 0x0100 /* ADC_VU */ > +#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */ > +#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */ > +#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */ > +#define WM8400_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ > +#define WM8400_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ > +#define WM8400_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ > + > +/* > + * R17 (0x11) - Right ADC Digital Volume > + */ > +#define WM8400_ADC_VU 0x0100 /* ADC_VU */ > +#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */ > +#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */ > +#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */ > +#define WM8400_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ > +#define WM8400_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ > +#define WM8400_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ > + > +/* > + * R18 (0x12) - GPIO CTRL 1 > + */ > +#define WM8400_IRQ 0x1000 /* IRQ */ > +#define WM8400_IRQ_MASK 0x1000 /* IRQ */ > +#define WM8400_IRQ_SHIFT 12 /* IRQ */ > +#define WM8400_IRQ_WIDTH 1 /* IRQ */ > +#define WM8400_TEMPOK 0x0800 /* TEMPOK */ > +#define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */ > +#define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */ > +#define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */ > +#define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */ > +#define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */ > +#define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */ > +#define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */ > +#define WM8400_MIC1DET 0x0200 /* MIC1DET */ > +#define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */ > +#define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */ > +#define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */ > +#define WM8400_FLL_LCK 0x0100 /* FLL_LCK */ > +#define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */ > +#define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */ > +#define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */ > +#define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */ > +#define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */ > +#define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */ > + > +/* > + * R19 (0x13) - GPIO1 & GPIO2 > + */ > +#define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ > +#define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */ > +#define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */ > +#define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */ > +#define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ > +#define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */ > +#define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */ > +#define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */ > +#define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */ > +#define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */ > +#define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */ > +#define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ > +#define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */ > +#define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */ > +#define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */ > +#define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ > +#define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ > +#define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */ > +#define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */ > +#define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ > +#define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */ > +#define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */ > +#define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */ > +#define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ > +#define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */ > +#define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */ > +#define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */ > +#define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */ > +#define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ > +#define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ > +#define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ > +#define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */ > +#define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ > +#define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ > +#define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ > +#define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ > +#define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ > +#define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ > + > +/* > + * R20 (0x14) - GPIO3 & GPIO4 > + */ > +#define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ > +#define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */ > +#define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */ > +#define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */ > +#define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ > +#define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */ > +#define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */ > +#define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */ > +#define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */ > +#define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */ > +#define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */ > +#define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */ > +#define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */ > +#define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */ > +#define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */ > +#define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */ > +#define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ > +#define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */ > +#define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */ > +#define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ > +#define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */ > +#define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */ > +#define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */ > +#define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ > +#define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */ > +#define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */ > +#define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */ > +#define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */ > +#define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ > +#define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ > +#define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ > +#define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */ > +#define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ > +#define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ > +#define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ > +#define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ > +#define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ > +#define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ > + > +/* > + * R21 (0x15) - GPIO5 & GPIO6 > + */ > +#define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ > +#define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */ > +#define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */ > +#define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */ > +#define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ > +#define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */ > +#define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */ > +#define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */ > +#define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */ > +#define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */ > +#define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */ > +#define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */ > +#define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */ > +#define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */ > +#define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */ > +#define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */ > +#define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ > +#define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */ > +#define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */ > +#define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ > +#define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */ > +#define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */ > +#define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */ > +#define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ > +#define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */ > +#define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */ > +#define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */ > +#define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */ > +#define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */ > +#define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */ > +#define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */ > +#define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */ > +#define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */ > +#define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */ > +#define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */ > +#define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ > +#define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */ > +#define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */ > + > +/* > + * R22 (0x16) - GPIOCTRL 2 > + */ > +#define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ > +#define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */ > +#define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */ > +#define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */ > +#define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */ > +#define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */ > +#define WM8400_MIC1SHRT_IRQ_ENA


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Re: [PATCH 1/2] mfd: Core support for the WM8400 AudioPlus HiFi CODEC and PMU

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