> > newer controllers support the 32bit PIO data cycles. Most PCI controllers
quoted text
> > it makes no speed difference but host bus controllers (especially
> > PIIX/ICH) really benefit.
> >   
> 
>     In what way if there's no speed gain?

As in the numbers are the same before and after. The FIFO on the
controller is happily hiding the extra latencies I assume.

quoted text
> >> supported. I couldn't track down where that bit was actually defined in 
> >> the first place, all the way back to ATA-1 it seems to be indicated as 
> >> reserved. Actually, I'm not sure why the drive cares in the first place, 
> >> it would seem like a pure host controller issue..
> >>     
> >
> > It goes back before IDE into the depths of the original compaq spec. When
> > you have a device wired basically directly to the ISA bus (original IDE)
> >   
> 
>    ISA has only 8/16-bit data bus, so it could not have mattered 
> there... 

Depends what a 32bit I/O looks like on the 16bit bus - timing wise.
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