Yinghai Lu wrote:
quoted text
>>> cpu is going to check that vectors in addition to vectors in IDT?
>> No. The destination cpu and destination vector number are encoded in
>> the MSI message.  Each MSI-X source ``vector'' has a different MSI message.
>>
>> So on my wish list is to stably encode the MSI interurrpt numbers.  And
>> using a sparse irq address space I can.  As it only takes 28 bits to hold
>> the complete bus + device + function + msi source [ 0-4095 ]
> 
> how about ioapic interrupt numbers...? they should stay with same
> numbering with gsi?
> 
> and how about pci segments : that will need another 4 bits for AMD
> systems..aka 16 segments..
> 
> you will run out of 32bits...
> 

I also see little value in stably encoding IRQ numbers using 
geographical identifiers.  It seems that the only case where you care 
that an interrupt number is stable is when it is *not* tied to a 
geographically addressed entity, so why does it matter?

	-hpa
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