RE: [PATCH 01/01][retry 3] x86: L3 cache index disable for 2.6.26

!MAILaRCHIVE_VOTE_RePLACE
Previous message: [thread] [date] [author]
Next message: [thread] [date] [author]
To: Pavel Machek <pavel@...>
Cc: Greg KH <greg@...>, Deguara, Joachim <joachim.deguara@...>, <gregkh@...>, <tglx@...>, <mingo@...>, <hpa@...>, <linux-kernel@...>
Date: Thursday, August 14, 2008 - 10:02 am

> > +

The strlen can go - it's no longer necessary.

If sscanf isn't safe in this context, there's a lot of code
in drivers/cpufreq/cpufreq.c that I cribbed from that needs
to be changed, too.
 

I don't think so.  If it got this far, it is an AMD processor
from family 0x10 or later, so it has wbinvd().

-Mark Langsdorf
Operating System Research Center
AMD

--
Previous message: [thread] [date] [author]
Next message: [thread] [date] [author]

Messages in current thread:
[PATCH 01/01] x86: L3 cache index disable for 2.6.26, Mark Langsdorf, (Fri Jul 18, 5:03 pm)
RE: [PATCH 01/01][retry 3] x86: L3 cache index disable for 2..., Langsdorf, Mark, (Thu Aug 14, 10:02 am)
Re: [PATCH 01/01] x86: L3 cache index disable for 2.6.26, Mark Langsdorf, (Tue Jul 22, 2:06 pm)
RE: [PATCH 01/01] x86: L3 cache index disable for 2.6.26, Langsdorf, Mark, (Mon Jul 28, 10:54 am)