Hi,
On Fri, 2008-08-01 at 17:05 -0400, ext Len Brown wrote:

[snip]

quoted text
> Memory power management
> -----------------------
> 
> We discussed the challenges to memory power management
> on servers.  Specifically, power-friendly interleaving
> and the inability to migrate/free pages used by the kernel.
> 
> HSuperH may benefit soonest here b/c
> not stopped by interleaving issue.
> NUMA memory node for accounting.
> 
> Paul Mundt, using on SH
> needs to be dynamic b/c cores turned on/off dynamically.
> 
> This is a common requirement between embedded and server platform
> Consensus was to work on a common framework for page
> placement based on frequency of reference.
> 
> Physical address to memory module (DIMM) information needs to be
> exported by the platform to get started on any memory PM techniques.
> Currently there is no information about fine grain memory topology
> except for NUMA systems at node level.

I am interested about the embedded part: last year Nokia had an
evaluation done on the memory chip used for n800, which can be set to
perform self refresh of 1/4, 1/2 and 1/1 of the available SDRAM.

The finding was that on average the energy spent for rearranging the
pages so that those going to be preserved would be in the memory area
kept in self refresh + the energy spent for reloading the other pages
from flash was significantly higher than just using self refresh for the
entire SDRAM.

I can dig out the details if there is interest, however the SDRAM used
is the mobile type with relatively low leakages and speed (133MHz).

I'd be interested to know what's the case with SH and if there has been
any study/verification.

-- 

Cheers, Igor

---

Igor Stoppa
Maemo Software - Nokia Devices R&D - Helsinki
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