RE: [PATCH 3/6] AMD IOMMU: flush domain TLB when there is more than onepage to flush

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From: Duran, Leo
Date: Thursday, July 3, 2008 - 11:01 am

On Thursday, July 03, 2008 12:35 PM, Joerg Roedel wrote:

When

Joerg,

Instead of flushing the complete TLB, how about just setting the
page-size encoding bits so as to cover all of the pages (rounded up to a
power of 2... which in some cases may flush a few more pages, but not
the complete TLB). This way other devices don't pay the 'flushing'
penalty every time you unmap a buffer for a given device.

Leo.

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Messages in current thread:
[PATCH 0/6] AMD IOMMU updates, Joerg Roedel, (Thu Jul 3, 10:35 am)
RE: [PATCH 3/6] AMD IOMMU: flush domain TLB when there is ..., Duran, Leo, (Thu Jul 3, 11:01 am)
Re: [PATCH 0/6] AMD IOMMU updates, Ingo Molnar, (Fri Jul 4, 2:52 am)
Re: [PATCH 0/6] AMD IOMMU updates, FUJITA Tomonori, (Mon Jul 7, 12:40 am)
Re: [PATCH 0/6] AMD IOMMU updates, Ingo Molnar, (Mon Jul 7, 12:44 am)