[PATCH v2] documentation: move mtrr.txt to Doc/x86/ subdir

Previous thread: [GIT PULL] dlm updates for 2.6.27 (resend) by David Teigland on Tuesday, July 22, 2008 - 9:40 am. (1 message)

Next thread: Firmware breakage by Alan Cox on Tuesday, July 22, 2008 - 9:34 am. (8 messages)
From: Randy Dunlap
Date: Tuesday, July 22, 2008 - 9:48 am

From: Randy Dunlap <randy.dunlap@oracle.com>

Move mtrr.txt to the Documentation/x86/ subdirectory.
Add 00-INDEX to the Documentation/x86/ subdirectory.

Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
---
 Documentation/00-INDEX     |    2 
 Documentation/mtrr.txt     |  305 ---------------------------------------------
 Documentation/x86/00-INDEX |    4 
 Documentation/x86/mtrr.txt |  305 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 309 insertions(+), 307 deletions(-)

--- lin2626-git9.orig/Documentation/mtrr.txt
+++ /dev/null
@@ -1,305 +0,0 @@
-MTRR (Memory Type Range Register) control
-3 Jun 1999
-Richard Gooch
-<rgooch@atnf.csiro.au>
-
-  On Intel P6 family processors (Pentium Pro, Pentium II and later)
-  the Memory Type Range Registers (MTRRs) may be used to control
-  processor access to memory ranges. This is most useful when you have
-  a video (VGA) card on a PCI or AGP bus. Enabling write-combining
-  allows bus write transfers to be combined into a larger transfer
-  before bursting over the PCI/AGP bus. This can increase performance
-  of image write operations 2.5 times or more.
-
-  The Cyrix 6x86, 6x86MX and M II processors have Address Range
-  Registers (ARRs) which provide a similar functionality to MTRRs. For
-  these, the ARRs are used to emulate the MTRRs.
-
-  The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
-  MTRRs. These are supported.  The AMD Athlon family provide 8 Intel
-  style MTRRs.
-  
-  The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. These
-  are supported.
-
-  The VIA Cyrix III and VIA C3 CPUs offer 8 Intel style MTRRs.
-
-  The CONFIG_MTRR option creates a /proc/mtrr file which may be used
-  to manipulate your MTRRs. Typically the X server should use
-  this. This should have a reasonably generic interface so that
-  similar control registers on other processors can be easily
-  supported.
-
-
-There are two interfaces to /proc/mtrr: one is an ASCII ...
From: Adrian Bunk
Date: Friday, July 25, 2008 - 2:02 pm

cu
Adrian

-- 

       "Is there not promise of rain?" Ling Tan asked suddenly out
        of the darkness. There had been need of rain for many days.
       "Only a promise," Lao Er said.
                                       Pearl S. Buck - Dragon Seed

--

From: Randy Dunlap
Date: Saturday, July 26, 2008 - 5:54 pm

> Please also update the path in arch/x86/Kconfig

Yes.  Thanks, Adrian.

---

From: Randy Dunlap <randy.dunlap@oracle.com>

Move mtrr.txt to the Documentation/x86/ subdirectory.
Add 00-INDEX to the Documentation/x86/ subdirectory.

Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
---
 Documentation/00-INDEX     |    2 
 Documentation/mtrr.txt     |  305 ---------------------------------------------
 Documentation/x86/00-INDEX |    4 
 Documentation/x86/mtrr.txt |  305 +++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/Kconfig           |    2 
 5 files changed, 310 insertions(+), 308 deletions(-)

--- lin2626-g9-kerndoc.orig/Documentation/mtrr.txt
+++ /dev/null
@@ -1,305 +0,0 @@
-MTRR (Memory Type Range Register) control
-3 Jun 1999
-Richard Gooch
-<rgooch@atnf.csiro.au>
-
-  On Intel P6 family processors (Pentium Pro, Pentium II and later)
-  the Memory Type Range Registers (MTRRs) may be used to control
-  processor access to memory ranges. This is most useful when you have
-  a video (VGA) card on a PCI or AGP bus. Enabling write-combining
-  allows bus write transfers to be combined into a larger transfer
-  before bursting over the PCI/AGP bus. This can increase performance
-  of image write operations 2.5 times or more.
-
-  The Cyrix 6x86, 6x86MX and M II processors have Address Range
-  Registers (ARRs) which provide a similar functionality to MTRRs. For
-  these, the ARRs are used to emulate the MTRRs.
-
-  The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
-  MTRRs. These are supported.  The AMD Athlon family provide 8 Intel
-  style MTRRs.
-  
-  The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. These
-  are supported.
-
-  The VIA Cyrix III and VIA C3 CPUs offer 8 Intel style MTRRs.
-
-  The CONFIG_MTRR option creates a /proc/mtrr file which may be used
-  to manipulate your MTRRs. Typically the X server should use
-  this. This should have a reasonably generic interface so that
-  similar control registers ...
Previous thread: [GIT PULL] dlm updates for 2.6.27 (resend) by David Teigland on Tuesday, July 22, 2008 - 9:40 am. (1 message)

Next thread: Firmware breakage by Alan Cox on Tuesday, July 22, 2008 - 9:34 am. (8 messages)