I wouldn't worry too much - it's going to be pretty visible anyway.
The only thing I _would_ worry about is the AMD prefetch bug - some AMD
cores raise a spurious page fault for prefetch instructions, and we ignore
it.
I _think_ that bug is a pure TLB issue and would never trigger for an
address that doesn't do page fault handling at all because it gets caught
in the "is the address valid" code, but it does make me go "Hmm".
See
http://lkml.org/lkml/2003/9/10/397
from Rich Brunner. The AMD errata listing does say just page fault, and
does talk about speculative TLB reloads, so I think we're all good.
Linus
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