Cc: Ingo Molnar <mingo@...>, David Howells <dhowells@...>, Ulrich Drepper <drepper@...>, Linux Kernel Mailing List <linux-kernel@...>, Andrew Morton <akpm@...>
I'd be *very* nervous about this.
Yes and no.
Yes, the bits are int he same word, so cache coherency guarantees a lot.
HOWEVER. If you do the sub-word write using a regular store, you are now
invoking the _one_ non-coherent part of the x86 memory pipeline: the store
buffer. Normal stores can (and will) be forwarded to subsequent loads from
the store buffer, and they are not strongly ordered wrt cache coherency
while they are buffered.
IOW, on x86, loads are ordered wrt loads, and stores are ordered wrt other
stores, but loads are *not* ordered wrt other stores in the absense of a
serializing instruction, and it's exactly because of the write buffer.
So:
See above. The above is unsafe, because if you do a regular store to a
partial word, with no serializing instructions between that and a
subsequent load of the whole word, the value of the store can be bypassed
from the store buffer, and the load from the other part of the word can be
carried out _before_ the store has actually gotten that cacheline
exclusively!
So when you do
movb reg,(byteptr)
movl (byteptr),reg
you may actually get old data in the upper 24 bits, along with new data in
the lower 8.
I think.
Anyway, be careful. The cacheline itself will always be coherent, but the
store buffer is not going to be part of the coherency rules, and without
serialization (or locked ops), you _are_ going to invoke the store buffer!
Linus
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