Cc: Russell King <rmk+lkml@...>, Linus Torvalds <torvalds@...>, David Miller <davem@...>, <linux-arch@...>, <scottwood@...>, <linuxppc-dev@...>, <alan@...>, <linux-kernel@...>, <tpiepho@...>
> This whole thread also ties in with my posts about mmiowb (which IMO
In addition, some archs like powerpc also provide readl_be/writel_be as
being defined as big endian (ie. byteswap on LE archs, no byteswap on BE
archs).
As of today, powerpc lacks the raw_readl/raw_writel and __readl/__writel
variants (ie, we only provide fully ordered + byteswap and no ordering +
no byteswap variants).
If we agree on the above semantics, I'll do a patch providing the
missing ones.
The ordering guarantees that I provide on powerpc for "ordered" variants
are:
- cacheable store + writel stays ordered (ie, write to some
DMA stuff and then a register to trigger the DMA).
- readl + cacheable read stays ordered (ie. read some status
register, for example, after an interrupt, and then read the
resulting data in memory).
- any of these ordered vs. spin_lock and spin_unlock (with the
exception that stores done before the spin_lock
could potentially leak into the lock).
- readl is synchronous (ie, makes the CPU think the
data was actually used before executing subsequent
instructions, thus waits for the data to come back,
for example to ensure that a read used to push out
post buffers followed by a delay will indeed happen
with the right delay).
We don't provide meaningless ones like writel + cacheable store for
example. (PCI posting would defeat it anyway).
Ben.
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