On Tuesday, June 24, 2008 3:46 am David Vrabel wrote:
quoted text
> PCI MSI interrupts are masked and unmasked using a method (by writing
> the MSI Enable capability bit) that is prohibited by the PCI specification.

Yeah, it's probably quite a bit slower too (I assume you're talking about 
io_apic_64's msi_mask_irq).  Seems like masking this at the ioapic level 
would make more sense anyway...

quoted text
> This behaviour can cause missed interrupts with some devices if the
> interrupt is asserted by the hardware while MSI is disabled.
>
> I believe the interrupt should be masked/unmasked on the interrupt
> controller (the APIC on x86, for example).   I'm going to test this now
> and see if it works.

Great, thanks.

Jesse
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