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[patch 05/10] x86: set PAE PHYSICAL_MASK_SHIFT to 44 bits.

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From: Greg KH <gregkh@...>
To: <linux-kernel@...>, <stable@...>, <jejb@...>
Cc: Justin Forbes <jmforbes@...>, Zwane Mwaikambo <zwane@...>, Theodore Ts'o <tytso@...>, Randy Dunlap <rdunlap@...>, Dave Jones <davej@...>, Chuck Wolber <chuckw@...>, Chris Wedgwood <reviews@...>, Michael Krufky <mkrufky@...>, Chuck Ebbert <cebbert@...>, Domenico Andreoli <cavokz@...>, Willy Tarreau <w@...>, Rodrigo Rubira Branco <rbranco@...>, <torvalds@...>, <akpm@...>, <alan@...>, Jeremy Fitzhardinge <jeremy.fitzhardinge@...>, Jan Beulich <jbeulich@...>, Ingo Molnar <mingo@...>
Subject: [patch 05/10] x86: set PAE PHYSICAL_MASK_SHIFT to 44 bits.
Date: Monday, June 23, 2008 - 7:04 pm

2.6.25.9-stable review patch.  If anyone has any objections, please let
us know.

------------------ 
From: Jeremy Fitzhardinge <jeremy@goop.org>

commit ad524d46f36bbc32033bb72ba42958f12bf49b06 upstream

When a 64-bit x86 processor runs in 32-bit PAE mode, a pte can
potentially have the same number of physical address bits as the
64-bit host ("Enhanced Legacy PAE Paging").  This means, in theory,
we could have up to 52 bits of physical address in a pte.

The 32-bit kernel uses a 32-bit unsigned long to represent a pfn.
This means that it can only represent physical addresses up to 32+12=44
bits wide.  Rather than widening pfns everywhere, just set 2^44 as the
Linux x86_32-PAE architectural limit for physical address size.

This is a bugfix for two cases:
1. running a 32-bit PAE kernel on a machine with
  more than 64GB RAM.
2. running a 32-bit PAE Xen guest on a host machine with
  more than 64GB RAM

In both cases, a pte could need to have more than 36 bits of physical,
and masking it to 36-bits will cause fairly severe havoc.

Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Cc: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

---
 include/asm-x86/page_32.h |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

--- a/include/asm-x86/page_32.h
+++ b/include/asm-x86/page_32.h
@@ -14,7 +14,8 @@
 #define __PAGE_OFFSET		_AC(CONFIG_PAGE_OFFSET, UL)
 
 #ifdef CONFIG_X86_PAE
-#define __PHYSICAL_MASK_SHIFT	36
+/* 44=32+12, the limit we can fit into an unsigned long pfn */
+#define __PHYSICAL_MASK_SHIFT	44
 #define __VIRTUAL_MASK_SHIFT	32
 #define PAGETABLE_LEVELS	3
 

-- 
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Messages in current thread:
[patch 00/10] 2.6.28.9-rc2 review, Greg KH, (Mon Jun 23, 7:04 pm)
Re: [patch 00/10] 2.6.28.9-rc2 review, Greg KH, (Mon Jun 23, 7:22 pm)
[patch 04/10] x86: use BOOTMEM_EXCLUSIVE on 32-bit, Greg KH, (Mon Jun 23, 7:05 pm)
[patch 03/10] sctp: Make sure N * sizeof(union sctp_addr) do..., Greg KH, (Mon Jun 23, 7:05 pm)
[patch 02/10] Reinstate ZERO_PAGE optimization in get_user_p..., Greg KH, (Mon Jun 23, 7:05 pm)
[patch 01/10] atl1: relax eeprom mac address error check, Greg KH, (Mon Jun 23, 7:05 pm)
[patch 07/10] watchdog: hpwdt: fix use of inline assembly, Greg KH, (Mon Jun 23, 7:05 pm)
[patch 06/10] Add return value to reserve_bootmem_node(), Greg KH, (Mon Jun 23, 7:04 pm)
Re: [patch 06/10] Add return value to reserve_bootmem_node(), Adrian Bunk, (Tue Jun 24, 7:06 am)
Re: [patch 06/10] Add return value to reserve_bootmem_node(), Greg KH, (Tue Jun 24, 5:07 pm)
[patch 05/10] x86: set PAE PHYSICAL_MASK_SHIFT to 44 bits., Greg KH, (Mon Jun 23, 7:04 pm)
[patch 10/10] Fix ZERO_PAGE breakage with vmware, Greg KH, (Mon Jun 23, 7:04 pm)
Re: [patch 10/10] Fix ZERO_PAGE breakage with vmware, Linus Torvalds, (Mon Jun 23, 7:28 pm)
Re: [patch 10/10] Fix ZERO_PAGE breakage with vmware, Greg KH, (Tue Jun 24, 2:04 am)
[patch 09/10] hwmon: (adt7473) Initialize max_duty_at_overhe..., Greg KH, (Mon Jun 23, 7:04 pm)
[patch 08/10] hwmon: (lm85) Fix function RANGE_TO_REG(), Greg KH, (Mon Jun 23, 7:04 pm)