On Wed, 18 Jun 2008, Rafael J. Wysocki wrote:Thanks -- this is very important and useful information as it shows the exact alternative used. With such a configuration the "x86: I/O APIC: timer through 8259A second-chance" patch should not matter, because the only change it introduces is an attempt to try the same I/O APIC pin again, but with the IRQ0 line of the master 8259A enabled. That's not a terribly unusual configuration and nothing should get confused in the system. Barring the unlikely possibility of the 8259A actually being wired to INTIN2 of the I/O APIC I can see two possible explanations: 1. The 8259A interrupt actually escapes to the CPU somehow and is handled as an ExtINTA interrupt. This would make the code in check_timer() decide it has found a working configuration, while actually it has been fooled. 2. There is a bug in this patch or an assumption it makes which results in the state of some component not to be restored correctly. Unfortunately I have no resources to test the 64-bit variation of the code, so something may have escaped my attention. I'd like to find out which one is the case -- can you please reapply the patch and send me the corresponding section of the bootstrap log? If the system hangs before you can retrieve the log, please just place: while (1); or something like that after the out: label in check_timer(). Thanks. Maciej --
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