Cc: Paul Mackerras <paulus@...>, Matthew Wilcox <matthew@...>, Trent Piepho <tpiepho@...>, Russell King <rmk+lkml@...>, Benjamin Herrenschmidt <benh@...>, David Miller <davem@...>, <linux-arch@...>, <scottwood@...>, <linuxppc-dev@...>, <alan@...>, <linux-kernel@...>
Definitive? Dunno. But look in the Architecture manual, volume 3A, 10.3
"Methods of Caching Available", and then under the bullet about Write
Combining (WC), it says
the writes may be delayed until the next occurrence of a serializing
event; such as, an SFENCE of MFENCE instruction, CPUID execution, a read
or write to uncached memory, an interrupt occurrence, or a LOCK
instruction execution.
However, it's worth noting that
- documentation can be wrong, or even if right, can be Intel-specific.
- the above is expressly _only_ about the WC buffer, not about regular
memory writes. Cached memory accesses are different from WC accesses.
so in the end, the thing that matters is how things actually work.
Linus
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