On Thu, 08 May 2008 16:41:51 -0700
Alexis Bruemmer <alexisb@us.ibm.com> wrote:

quoted text
> On Fri, 2008-05-09 at 08:13 +0900, FUJITA Tomonori wrote:
> > On Thu, 08 May 2008 14:40:20 -0700
> > Alexis Bruemmer <alexisb@us.ibm.com> wrote:
> > 
> > > Currently the calgary code can give drivers addresses above 4GB which is
> > > very bad for hardware that is only 32bit DMA addressable.  This patch
> > > "teaches" calgary to fallback to the appropriate dma_ops when it
> > > encounters a device/bus which is not behind the Calgary/CalIOC2.  I
> > > believe there is a better way to do this and am open for ideas, but for
> > > now this certainly fixes the badness.
> > 
> > I'm not sure that I correctly understand what you want. You mean that
> > the Calgary IOMMU code ignores device's dma_mask and gives addresses
> > above 4GB or the Calgary IOMMU code wrongly handles devices that are
> > not behind the Calgary?
> The real issue is the latter-- the Calgary IOMMU code does not properly
> handle devices that are not behind the Calgary/CalIO2.

Thanks, now I see why you use swiotlb for such devices in the case of
end_pfn > MAX_DMA32_PFN and no_dma_ops works for them in the case of
of end_pfn < MAX_DMA32_PFN.

Can we put a pointer to dma_ops in struct device (archdata) like POWER
does? The way to setup and handle x86 IOMMUs seems to become hacky day
by day.
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