> > IE. Take an x86 version of that test, writing to memory, doing a writel
That brings us back to the old debate...
For consistent memory, should we mandate a wmb between write to some dma
data structure in consistent memory and the following mmio write that
trigger it, and the same goes with rmb and read ?
David, you remember we had those discussions a while back when I was
trying to relax a bit the barriers we have in our MMIO accessors on
powerpc, and the overwhelming answer was that x86 being in order, I have
to expect 90% of the drivers to not get any barrier right on any
platform, and thus I should make my MMIO accessors "look like" x86 and
thus ordered.
We did that, adding some barriers in the assembly of our readl/writel.
However, I didn't change the clobber, it's still *addr, not a full
"memory" clobber, just like x86.
Now if it appears that gcc can indeed re-order things, then we have a
problem on both x86, ppc, and pretty much everybody else. (I'm not sure
about sparc but I don't see any explicit clobber in your accessors
there).
So that brings the whole subject back imho. What should be the approach
here ? I see several options:
- mandate some kind of dma_sync_for_device/cpu on consistent memory.
Almost no driver do that currently tho. They only do that for non
consistent memory mapped with dma_map_*.
- mandate the use of wmb,rmb,mb barriers for use between memory
accesses and MMIOs for ordering them. (ie. fix drivers that don't do
it). Advantage for powerpc is that I can remove (after some auditing of
course) the added heavy barriers in the MMIO accessors themselves.
- stick a full memory clobber in all MMIO (and PIO) accessors on all
archs.
Any other idea ? preference ?
Cheers,
Ben.
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