> Here is a trace from pci express analyzer. I'm sending > 0x0800010000000000 to the adress DD1400C0 using writeq. Notice that in > the TLP header it sent a 32bit Memory write with data length of two. By the way, are you worried that there is something wrong with this trace? Your write went out in a single PCIe packet, so it looks perfect to me. Does the "Mem MWr(32)" worry you? I can't see why it would be a problem -- the PCIe TLP only has one type of memory write transaction (well, except for 32-bit or 64-bit addressing, but you don't care about that), and memory write transactions are sent as a string of 32-bit chunks, so there's no other way a 64-bit write could be sent. > Trace follows: > > Link Tra(597) Downstream 2.5(x1) TLP(1992) Mem MWr(32)(10:00000) TC(0) > TD(0) > _______| EP(0) Attributes(01) Length(2) RequesterID(000:02:0) Tag(8) > _______| Address(DD1400C0) 1st BE(1111) Last BE(1111) Data(08000100 > 00000000) > _______| VC ID(0) Explicit ACK(Packet #1195) Metrics # Packets(2) > _______| Time Stamp(0003 . 120 181 840 s) --
| Ingo Molnar | Re: containers (was Re: -mm merge plans for 2.6.23) |
| Greg Kroah-Hartman | [PATCH 009/196] Chinese: add translation of sparse.txt |
| holzheu | Re: [RFC/PATCH] Documentation of kernel messages |
| Vladislav Bolkhovitin | Re: Integration of SCST in the mainstream Linux kernel |
git: | |
| Jarek Poplawski | [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
| Gerrit Renker | [PATCH 27/37] dccp: Integration of dynamic feature activation - part 2 (server side) |
| David Miller | [GIT]: Networking |
| Antonio Almeida | HTB accuracy for high speed |
