Hello,

 I have released the perfmon2 kernel patch for kernel v2.6.25. There is
 no major features. However, there were a major restructuring of the code
 to make it more readable, isolate features per module. The header files
 have also been restructured to separate user vs. kernel, and generic only
 vs. shared with arch. The restructuring of the interrupt handler yielded
 a nice 15% latency improvement on single counter sampling runs on X86.
 This new structure will make it easier to extract features and merge them
 with the mainline kernel.

 In the time frame of 2.6.26, I will push a few bits and pieces to LKML
 for final review and integration.

 Here are some of the kernel changes:
  - Cell updates (Carl Love, Takashi Yamamoto)
  - new perfmon_debug boot option to enable debug (Robert Richter)
  - several bugs fixes on Itanium, MIPS and generic hrtimer management
  - Power locking updates (Corey Ashford)

 There is also a new release for libpfm, now at version 3.4.
 The changes include:
  - AMD Phenom (a.k.a. Barcelona) IBS support (Robert Richter)
  - Python bindings and examples (Arun Sharma)
  - environment variable support to enable debugging
  - auto-detection of syscall base number for 2.6.24 and 2.6.25
  - new multi-threaded self-sampling example (Mark W. Krentel)
  - man pages cleanups (Steve Kaufmann)

 Special thanks to Arun (Google). The Python bindings are a nice addition
 to libpfm especially for prototyping and writing testsuites.

 Finally, a new major version of pfmon, now at pfmon-3.4.
 Among the many changes:
  - added support for dmalloc (Andrzej Nowak)
  - updated support for Cell processor (Takashi Yamamoto)
  - possibility to terminate pfmon cleanly with SIGTERM
  - --follow-fork and derivatives fixed on Itanium and other platforms
  - tracking of dlopen now works on mixed ABI environments
  - lots of bugs fixes

 As usual all files and more detailed changelogs can be downloaded from our
 website at:

        http://perfmon.sourceforge.net

...
[ message continues ]

Hello,


Several people noticed there was a typo in the website url.
The actual web site is:

      http://perfmon2.sf.net


Sorry about that.

On Tue, Apr 29, 2008 at 11:47 PM, stephane eranian
--

On Tue, 29 Apr 2008 23:47:17 +0200

it hides well there ;(
the website seems to only offer a 2003 version for download.. I doubt that that is the right one..
--

Sorry,

It's http://perfmon2.sf.net



--

On Wed, 30 Apr 2008 15:11:11 +0200

hummmmm, I wonder why perfmon wants to reimplement half of the PCI layer...

+extern spinlock_t pci_config_lock;
+
+#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
+       (0x80000000 | ((reg & 0xF00) << 16) | ((bus & 0xFF) << 16) \
+       | (devfn << 8) | (reg & 0xFC))
+
+#define is_ibs_pmc(x) (x == 4 || x == 5)
+
+static int pci_read(unsigned int seg, unsigned int bus,
+                   unsigned int devfn, int reg, int len, u32 *value)
+{
+       unsigned long flags;

especially since this doesn't seem to use the proper config space abstractions :(
--

If I recall, AMD said that this special initialization would eventually migrate
into the core kernel. The pci_read() may be there because it was not exported
by the kernel (this particular code lives in a kernel module).

If you think there is now enough support in the core kernel to do this
initialization
then I'd be happy to remove this piece of code.




--

This patch implements PCI extended configuration space access for
AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
addresses. An x86 capability bit has been introduced that is set for
CPUs supporting PCI extended config space accesses.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/kernel/cpu/cpu.h |    3 +
 arch/x86/pci/Makefile_32  |    1 +
 arch/x86/pci/Makefile_64  |    2 +-
 arch/x86/pci/amd_bus.c    |  560 +++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/pci/direct.c     |   25 ++-
 arch/x86/pci/k8-bus_64.c  |  528 ------------------------------------------
 arch/x86/pci/pci.h        |    1 +
 7 files changed, 584 insertions(+), 536 deletions(-)
 create mode 100644 arch/x86/pci/amd_bus.c
 delete mode 100644 arch/x86/pci/k8-bus_64.c

diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 783691b..40ad189 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -1,3 +1,4 @@
+#ifdef CONFIG_X86_32
 
 struct cpu_model_info {
 	int vendor;
@@ -36,3 +37,5 @@ extern struct cpu_vendor_dev __x86cpuvendor_start[], __x86cpuvendor_end[];
 
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
+
+#endif /* CONFIG_X86_32 */
diff --git a/arch/x86/pci/Makefile_32 b/arch/x86/pci/Makefile_32
index 89ec35d..f647e7e 100644
--- a/arch/x86/pci/Makefile_32
+++ b/arch/x86/pci/Makefile_32
@@ -22,3 +22,4 @@ pci-$(CONFIG_X86_NUMAQ)		:= numa.o irq.o
 pci-$(CONFIG_NUMA)		+= mp_bus_to_node.o
 
 obj-y				+= $(pci-y) common.o early.o
+obj-y				+= amd_bus.o
diff --git a/arch/x86/pci/Makefile_64 b/arch/x86/pci/Makefile_64
index 8fbd198..fd47068 100644
--- a/arch/x86/pci/Makefile_64
+++ b/arch/x86/pci/Makefile_64
@@ -13,5 +13,5 @@ obj-y			+= legacy.o irq.o common.o early.o
 # mmconfig has a 64bit special
 obj-$(CONFIG_PCI_MMCONFIG) += mmconfig_64.o direct.o mmconfig-shared.o
 
-obj-y		+= k8-bus_64.o
+obj-y		+= ...
[ message continues ]

These patches are for the perfmon/master tree. They are based upon
tip/x86/cpu.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com

--

Robert,

This patch was applied to the perfmon GIT tree.
Please test.
Thanks.


--

It looks like the amd_bus.c file didn't get into the git tree. See the builds 
failing because of that.

-Will
--

Will,

Thanks for noticing this. I obviously forgot to invoke git add.
This should be fixed now.


--

This patch removes the workaround to access the Extended Config Space
that is needed to setup IBS interrupts. PCI functions are replaced by
standard PCI functions that support now ECS access.

Signed-off-by: Robert Richter <robert.richter@amd.com>
---
 arch/x86/pci/common.c            |    1 -
 arch/x86/perfmon/perfmon_amd64.c |  100 +------------------------------------
 2 files changed, 3 insertions(+), 98 deletions(-)

diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 400960b..6e64aaf 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -76,7 +76,6 @@ int pcibios_scanned;
  * configuration space.
  */
 DEFINE_SPINLOCK(pci_config_lock);
-EXPORT_SYMBOL(pci_config_lock);
 
 static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
 {
diff --git a/arch/x86/perfmon/perfmon_amd64.c b/arch/x86/perfmon/perfmon_amd64.c
index 6349e77..d8ad321 100644
--- a/arch/x86/perfmon/perfmon_amd64.c
+++ b/arch/x86/perfmon/perfmon_amd64.c
@@ -142,106 +142,12 @@ static struct pfm_context *pfm_nb_task_owner;
 
 static struct pfm_pmu_config pfm_amd64_pmu_conf;
 
-/* Functions for accessing extended PCI config space. Can be removed
-   when Kernel API exists. */
-extern spinlock_t pci_config_lock;
-
-#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
-	(0x80000000 | ((reg & 0xF00) << 16) | ((bus & 0xFF) << 16) \
-	| (devfn << 8) | (reg & 0xFC))
-
 #define is_ibs_pmc(x) (x == 4 || x == 5)
 
-static int pci_read(unsigned int seg, unsigned int bus,
-		    unsigned int devfn, int reg, int len, u32 *value)
-{
-	unsigned long flags;
-
-	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
-		*value = -1;
-		return -EINVAL;
-	}
-
-	spin_lock_irqsave(&pci_config_lock, flags);
-
-	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
-
-	switch (len) {
-	case 1:
-		*value = inb(0xCFC + (reg & 3));
-		break;
-	case 2:
-		*value = inw(0xCFC + (reg & 2));
-		break;
-	case 4:
-		*value = inl(0xCFC...
[ message continues ]

On Wed, 30 Apr 2008 15:51:39 +0200

... yet your patch adds an EXPORT_SYMBOL() just to make this specific function possible. Weird.

I find it hard to believe that there would be no code in the kernel to
read or write config space of a device you have..... :)
In fact I bet 80% of the drivers in the tree use it.

--

Access to extended config space for AMD northbridges was not yet
implemented. Recent patches from Yinghai Lu fix this. I will send a
patch that uses the in-kernel functions.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com

--