On Mon, 28 Apr 2008 10:29:08 -0400 James Bottomley <James.Bottomley@HansenPartnership.com> wrote:Cached means that the cpu, at any time, can do a speculative read to the memory. It also means that the cpu can then write the speculated cacheline back at any time later, if some speculation was going to write to the cacheline but didn't actually happen. (before you think this is bogus, at least AMD cpus do this and I can't vouch for Intel cpus never doing this). If the on-the-bus hardware *ever* writes to the memory without being part of the full cache coherence protocol it's in trouble. Big time. Even if it sends an invalidate first (which PCI and others just don't allow, not sure about MCA though), it's not enough because the cpu can just read it right back... one needs a "take for ownership" not an "invalidate" for this to work, and that means being part of the full protocol. that's write combining not cachability I suspect... at least for writes it is. x86 SoC ? (we're talking about an arch/x86 file here) Esp in SoC people don't bother doing cache coherency if they can get away with it. -- If you want to reach me at my work email, use arjan@linux.intel.com For development, discussion and tips for power savings, visit http://www.lesswatts.org --
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