James Bottomley wrote:
quoted text
>>> Yes, that's the one ... but I believe a class of the xAPICs also used a
>>> similar principle.
>> I certainly have never seen a system on which the APIC has been mapped 
>> cacheable.  I would be very interested in the details, so if you could 
>> elaborate that would be extremely useful.
> 
> Not really ... I just remember when the SAPIC and later the xAPIC
> details were published as novel nearly a decade ago, I remember saying
> that some of the voyager interrupt controllers had been using a similar
> method for years.
> 

Well, I just looked up the xAPIC spec, and it states very clearly:

APIC registers are memory-mapped to a 4-KByte region of the processor’s 
physical address space with an initial starting address of FEE00000H. 
For correct APIC operation, this address space must be mapped to an area 
of memory that has been designated as strong uncacheable (UC). See 
Section 10.3, “Methods of Caching Available.”

So any use of cacheline-related bus cycles is generated by the LAPIC and 
doesn't affect the CPU <-> LAPIC interface.

	-hpa


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