On Sun, 2008-04-27 at 15:13 -0700, H. Peter Anvin wrote:
quoted text
> James Bottomley wrote:
> > On Sun, 2008-04-27 at 15:00 -0700, H. Peter Anvin wrote:
> >> James Bottomley wrote:
> >>> I might add that the intel SAPIC functions
> >>> in roughly the same manner, so this might break more than just voyager.
> >> Are you referring to the IA64 SAPIC here, or something else?  The only 
> >> mention of SAPIC in the x86 tree appear to be naming of fields in ACPI 
> >> tables.
> > 
> > Yes, that's the one ... but I believe a class of the xAPICs also used a
> > similar principle.
> 
> I certainly have never seen a system on which the APIC has been mapped 
> cacheable.  I would be very interested in the details, so if you could 
> elaborate that would be extremely useful.

Not really ... I just remember when the SAPIC and later the xAPIC
details were published as novel nearly a decade ago, I remember saying
that some of the voyager interrupt controllers had been using a similar
method for years.

James


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