Mathieu Desnoyers wrote:
quoted text
> 
> Thinking about it, there could be a way to insure limited ZF and %al
> liveliness: adding an epilogue to the expected instruction sequence
> formed by an asm statement which clobbers the flags (flags are clobbered
> in any asm statement on x86) and clobbers %al.
> 
> From that point, we just have to find a specific signature that gcc
> could not imitate to put in this asm statement, so we can detect if
> other instructions have been placed in the middle of our sequence by
> gcc. Actually, I think the best thing to do with this asm statement is
> to put the instruction pointer in a special section, so we know that
> this code location marks the end of ZF and %al liveliness. There would
> be therefore no added code, just asm constraints.
> 
> This epilogue should then be used on both branches of the condition,
> like this :
> 
> if (unlikely(imv_cond(var))) {
>   imv_cond_end();
>   ...
> } else {
>   imv_cond_end();
>    ...
> }
> 

[...]

quoted text
> 
> Does it make sense ?
> 

I don't think so.  You're making way too many assumptions about the code 
generated by gcc.

This kind of stuff absolutely can be done, *BUT* it requires the 
cooperation of the compiler.  The right way to do this is to negotiate a 
set of appropriate builtins with the gcc people, and use them.  This 
means this optimization will only work when compiled with the new gcc, 
so there is a substantial lag, but it's the only sane way to do this 
kind of stuff.

	-hpa
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