On Wednesday 23 April 2008 05:46:49 pm Grant Grundler wrote:
My understanding of MWI is different. It concerns full cache line writes.
In that case the CPU can invalidate the cache line (without flushing it to
RAM). While in case of partial cache line writes, the processor should
flush the cache line before the controller writes to corresponding cached
address and then the controller finishes its partial cache line write to RAM.
In case MWI is NOT enables the CPU should flushe every cache line touched
by the controller's DMA machine, nevertheless it will be overwritten latter.
But, as usual, I could be wrong :-)
Agreed.
That is the reason why pci_set_mwi() and pci_try_set_mwi() exist.
Marin Mitov
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