> I thought the only pinned TLB entry was for the per cpu area? How does itPinning TLB entries on ia64 is done using TR registers with the "itr" instruction. Currently we have the following pinned mappings: itr[0] : maps kernel code. 64MB page at virtual 0xA000000100000000 dtr[1] : maps kernel data. 64MB page at virtual 0xA000000100000000 itr[1] : maps PAL code as required by architecture dtr[1] : maps an area of region 7 that spans kernel stack page size is kernel granule size (default 16M). This mapping needs to be reset on a context switch where we move to a stack in a different granule. We used to used dtr[2] to map the 64K per-cpu area at 0xFFFFFFFFFFFF0000 but Ken Chen found that performance was better to use a dynamically inserted DTC entry from the Alt-TLB miss handler which allows this entry in the TLB to be available for generic use (on most processor models). -Tony --
| debian developer | Re: Dual-Licensing Linux Kernel with GPL V2 and GPL V3 |
| Greg Kroah-Hartman | [PATCH 014/196] kobject: remove incorrect comment in kobject_rename |
| Vladislav Bolkhovitin | Re: Integration of SCST in the mainstream Linux kernel |
| Stephen Rothwell | Re: Announce: Linux-next (Or Andrew's dream :-)) |
git: | |
| Gerrit Renker | [PATCH 27/37] dccp: Integration of dynamic feature activation - part 2 (server side) |
| David Miller | [GIT]: Networking |
| Radu Rendec | htb parallelism on multi-core platforms |
| David Miller | Re: [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
