Hmm, it looks like the only one to be reasonably set under these
conditions, but I have never seen it reported for a read cycle to the EOI
register anyway, so I suppose it has to be a relatively recent addition.
Well, as I wrote, the error interrupt handler is always enabled,
reporting the state recorded in the ESR register as soon as an error
condition triggers and if an RMW cycle was a problem before, we would have
seen a flood of reports from people -- like we indeed have many times for
inter-APIC bus data corruption that triggers the same event (using bits
3:0 in the ESR as relevant).
Please note that ESR may hold some leftover state from whatever happened
before Linux has taken control, so it is reasonable and I think actually
recommended by Intel (FWIW) to clear the register before enabling the
error interrupt. For how to clear the ESR properly, please see
setup_local_APIC() -- subtle differences and errata in various APIC
implementations have made it more complicated than necessary, sigh...
Well, with CONFIG_X86_GOOD_APIC set there is no RMW access to the ESR as
apic_write_around() expands to apic_write(). And the option is meant to
be clear only for the original integrated APIC as included in the Pentium
processor ("Pentium-Classic" in the Kconfig nomenclature). I have no
means to test such a system, but I still have a working dual-Pentium-MMX
machine, which features local APICs that should be the same modulo errata.
I may check and see whether a RMW cycle to the ESR triggers any problems
with this computer, but the box is currently at the other end of the
continent, so it will take a while.
I have asked this question already: what kind of CPU are you running on?
Do you really need to have CONFIG_X86_GOOD_APIC clear with it?
Maciej
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