> I am familiar with that area and I am resonably sure that this 
quoted text
> is an issue on IA64 under some conditions (the processor decides to spill 
> some registers either onto the stack or into the register backing store 
> during tlb processing). Recursion (in the kernel context) still expects 
> the stack and register backing store to be available. ccing linux-ia64 for 
> any thoughts to the contrary.

Christoph is correct ... IA64 pins the TLB entry for the kernel stack
(which covers both the normal C stack and the register backing store)
so that it won't have to deal with a TLB miss on the stack while handling
another TLB miss.

-Tony
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