LAM> Also, does anyone have a VT6212L datasheet? Unfortunately, Google
I have eventually found it. An enlightening reading, really. If I 
understood all words, I mean :-). Particularly, what does "MAC turn around 
time" stand for with respect to EHCI? I would appreciate some reference, 
thanks.

  On Wed, 5 Mar 2008 at 5:19pm, Rene Herman wrote:

RH> It was diagnosed to the VT6212L doing decidedly weird things with
RH> toggling the Async bit and tying up the bus.
Yes, it really looks like the chip owns the bus when it shouldn't. Suppose 
VT6212L has damaged its brains somehow. Can we fix this by ignoring its 
requests unless they are legitimate? I mean make the driver enable bus 
mastering only for short periods when the controller is expected to do 
something useful. It is easy (I have already done myself) to implement for 
asynchronous schedule, but there's still periodic schedule. Is it 
possible? How? Please advise.

Being positive, I didn't have much time to play with it yet, but changing 
the bit 5 (EHCI sleep time select:  0=1us 1=10us) of register 0x4B seems 
to resolve my own problem. I wonder if this is going to help others 
(Alessandro?):

setpci -s 00:09.2 4b.b=29

[don't forget to adjust the device address].

-L
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