* Andi Kleen <andi@firstfloor.org> wrote:

quoted text
> [probably stable material too]
> 
> Use global TLB flushes in MTRR code
> 
> Obviously kernel mappings should be flushed here too.

no, your patch is not needed:

quoted text
>  	/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
> -	__flush_tlb();
> +	__flush_tlb_all();

read the complete code:

        /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
        if ( cpu_has_pge ) {
                cr4 = read_cr4();
                write_cr4(cr4 & ~X86_CR4_PGE);
        }

        /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
        __flush_tlb();

first first turn off PGE and do a cr3 flush - that gets rid of all TLBs.

but even if it didnt get rid of it, the mirror image function, 
post_set(), we turn PGE back on in the cr4 _after_ we've flushed the 
TLBs via the cr3 - that will flush all TLBs again.

	Ingo
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