* Andi Kleen <ak@suse.de> wrote:

quoted text
> e.g. the AMD64 pci-gart code sets pages not present to prevent 
> potential cache coherency problems.  When doing this it is probably 
> safer to flush the caches too. So consider clearing of the present bit 
> as a cache flush indicator.

uhm, but why? "Probably safer" is not the right kind of technical 
argument ;-)

The PCI-GART quirk which we use on some systems unmaps pages _not_ 
because of coherency problems (any cache coherency problems would be 
triggerable before we unmap them anyway), but due to _page aliasing_ 
problems: these pages might be in our general e820 map so we must 
disable them.

( in any case, the CPA code does not deal with cache attribute coherency 
  - that is topic of the upcoming PAT feature. We still largely rely on 
  MTRRs to get cache coherency right. )

furthermore, your patch does not even do what you claim it does, because
it is an elaborate NOP on most modern CPUs:

quoted text
> +static inline int cache_attr(pgprot_t set, pgprot_t clr)
>  {
> -	return pgprot_val(attr) &
> +	/*
> +	 * Clearing pages is usually done for cache cohereny reasons
> +	 * (except for pagealloc debug, but that doesn't call this anyways)
> +	 * It's safer to flush the caches in this case too.
> +	 */
> +	if (pgprot_val(clr) & _PAGE_PRESENT)
> +		return 1;

as clflush does not work on not present pages...

	Ingo
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