The specification of SS in the public manuals is a little unclear,
but I got confirmation from Intel that SS implies that there is no cache
flush needed on caching attribute changes.
Signed-off-by: Andi Kleen <ak@suse.de>
---
arch/x86/mm/pageattr.c | 5 ++++-
include/asm-x86/cpufeature.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
Index: linux/arch/x86/mm/pageattr.c
===================================================================
--- linux.orig/arch/x86/mm/pageattr.c
+++ linux/arch/x86/mm/pageattr.c
@@ -60,7 +60,7 @@ static void __cpa_flush_all(void *arg)
*/
__flush_tlb_all();
- if (boot_cpu_data.x86_model >= 4)
+ if (!cpu_has_ss && boot_cpu_data.x86_model >= 4)
wbinvd();
}
@@ -91,6 +91,9 @@ static void cpa_flush_range(unsigned lon
on_each_cpu(__cpa_flush_range, NULL, 1, 1);
+ if (cpu_has_ss)
+ return;
+
/*
* We only need to flush on one CPU,
* clflush is a MESI-coherent instruction that
Index: linux/include/asm-x86/cpufeature.h
===================================================================
--- linux.orig/include/asm-x86/cpufeature.h
+++ linux/include/asm-x86/cpufeature.h
@@ -153,6 +153,7 @@
#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
+#define cpu_has_ss boot_cpu_has(X86_FEATURE_SELFSNOOP)
#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
--
