On Tuesday 18 November 2008 13:08, Linus Torvalds wrote:

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> On Tue, 18 Nov 2008, Paul Mackerras wrote:

> > Also, you didn't respond to my comments about the purely software

> > benefits of a larger page size.

>

> I realize that there are benefits. It's just that the downsides tend to

> swamp the upsides.

>

> The fact is, Intel (and to a lesser degree, AMD) has shown how hardware

> can do good TLB's with essentially gang lookups, giving almost effective

> page sizes of 32kB with hardly any of the downsides. Couple that with

It's much harder to do this with powerpc I think because they would need

to calculate 8 hashes and touch 8 cachelines to prefill 8 translations,

wouldn't they?
> low-latency fault handling (for not when you miss in the TLB, but when

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> something really isn't in the page tables), and it seems to be seldom the

> biggest issue.

>

> (Don't get me wrong - TLB's are not unimportant on x86 either. But on x86,

> things are generally much better).

The per-page processing costs are interesting too, but IMO there is more

work that should be done to speed up order-0 pages. The patches I had to

remove the sync instruction for smp_mb() in unlock_page sped up pagecache

throughput (populate, write(2), reclaim) on my G5 by something really

crazy like 50% (most of that's in, but I'm still sitting on that fancy

unlock_page speedup to remove the final smp_mb).
I suspect some of the costs are also in powerpc specific code to insert

linux ptes into their hash table. I think some of the synchronisation for

those could possibly be shared with generic code so you don't need the

extra layer of locks there.

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