From 9a083f0e9a81f5bc31ea49f37112f1945830fc7c Mon Sep 17 00:00:00 2001
From: Matthew Fleming <matthew.fleming@imgtec.com>
Date: Thu, 2 Oct 2008 12:24:05 +0100
Subject: [PATCH 2/2] MMC: CSD and CID timeout values

The MMC spec states that the timeout for accessing the CSD and CID
registers is 64 clock cycles.

Signed-off-by: Matthew Fleming <matthew.fleming@imgtec.com>
---
 drivers/mmc/core/mmc_ops.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 64b05c6..9c50e6f 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -248,8 +248,12 @@ mmc_send_cxd_data(struct mmc_card *card, struct
mmc_host *host,

        sg_init_one(&sg, data_buf, len);

-       if (card)
-               mmc_set_data_timeout(&data, card);
+       /*
+        * The spec states that CSR and CID accesses have a timeout
+        * of 64 clock cycles.
+        */
+       data.timeout_ns = 0;
+       data.timeout_clks = 64;

        mmc_wait_for_req(host, &mrq);

--
1.5.5.2