--- On Mon, 1/28/08, Robert Hancock <hancockr@shaw.ca> wrote:
Can you double check this with the HW architect of the
HW DMA engine of the ASIC?
If this is indeed the case as you've presented it here,
it sounds like a HW shortcoming. I cannot see how the device
type (or protocol) dictate how the DMA engine operates.
They live in two different domains.
The reason for this is that the object that a struct scsi_dev
represents has nothing to do with HW DMA engines.
It looks like your current solution is correct and
x86_64's blk_queue_bounce_limit needs work.
Luben
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