* Andi Kleen <andi@firstfloor.org> wrote:

quoted text
> Ingo Molnar <mingo@elte.hu> writes:
> >
> > what we should probably do instead is to have a filter function:
> >
> >    new_end = trim_range_to_mtrr_cached(start, end);
> >
> > and then we could iterate through every e820 map entry that is 
> > marked as usable RAM, and send it through this filter. If the filter 
> > returns the same value that got passed in, we keep the e820 entry 
> > unchanged. If the filter returns a new "end" value, we use that in 
> > the e820 map.
> 
> To be fully generic you would need to allow it to adjust start too.

no, to be fully generic it would have to be able to 'split' e820 entries 
up and punch holes into them - but we dont want to go that far i think. 
The most common problem is mismatch at the end of a range.

but what matters more is to have full, generic _detection_ of the 
problem - and that's what we dont do right now. (and that's what my 
reply outlines)

The _fixup_ which we base on this information can then be anything from 
"trivially trim the end" up to a complex "punch holes" solution or the 
simplest "print nasty warning message and do nothing else" solution.

quoted text
> > that way, the current Tom2 hack is just a natural extension to the 
> > filter function: it would (on AMD CPUs) recognize (within 
> > trim_range_to_mtrr_cached filter) that all memory addresses above 
> > 4GB are marked as cacheable via Tom2.
> >
> > Or something like this. Hm?
> 
> I agree that would be the correct way to do it.
> 
> Later on with PAT that filter could also do PAT related checks and 
> something like this will likely be needed anyways.

a "what is the effective MTRR caching attribute of this physical 
address" type of function would benefit PAT too, yes.

	Ingo
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