Ingo Molnar <mingo@elte.hu> writes:
quoted text
>
> what we should probably do instead is to have a filter function:
>
>    new_end = trim_range_to_mtrr_cached(start, end);
>
> and then we could iterate through every e820 map entry that is marked as 
> usable RAM, and send it through this filter. If the filter returns the 
> same value that got passed in, we keep the e820 entry unchanged. If the 
> filter returns a new "end" value, we use that in the e820 map.

To be fully generic you would need to allow it to adjust start too.

quoted text
> that way, the current Tom2 hack is just a natural extension to the 
> filter function: it would (on AMD CPUs) recognize (within 
> trim_range_to_mtrr_cached filter) that all memory addresses above 4GB 
> are marked as cacheable via Tom2.
>
> Or something like this. Hm?

I agree that would be the correct way to do it.

Later on with PAT that filter could also do PAT related checks
and something like this will likely be needed anyways.

-Andi
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