Cc: Jeremy Fitzhardinge <jeremy@...>, Ingo Molnar <mingo@...>, Mika Penttilä <mika.penttila@...>, <linux-kernel@...>, Thomas Gleixner <tglx@...>, Ingo Molnar <mingo@...>, Eric W. Biederman <ebiederm@...>
This is part of the trickiness with re-using the early pagetables
instead of rebuilding them from scratch - if PSE is available, we have
two options:
- either we build PSE page tables early (which means detecting PSE,
which means if there are any chip-specific CPUID workarounds they have
to be present in the early code), or
- when building the "complete" page tables, coalesce !PSE pagetables
into PSE entries where appropriate.
For PAT to work right, the first chunk probably should *not* be a PSE
page table, which complicates things further. (There is no TLB impact,
since a PSE page table at offset zero or that otherwise have an MTRR
conflict will be broken apart in hardware.) In the former case, it
means splitting it apart later; in the latter case it just means
excluding it from coalescing.
In other words, reusing the early page tables isn't all that
straightforward. It may easily be that it's better to build a new set
of page tables from scratch, however, it would *still* be beneficial to
have the early page tables be in the same format as the later one, since
it lets us use the fixmap area, and therefore {bt,early}_ioremap() much
sooner.
-hpa
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