This is the matrix the CPU uses when combining MTRR and PAT behaviour.
It probably makes sense to mimic:
| WB WT WC UC
---+---------------
WB | WB WT WC UC
WT | WT WT UC UC
WC | WC UC WC UC
UC | UC UC UC UC
With the current PAT encoding:
WB = 00
WT = 01
WC = 10
UC = 11
... this is simply a bitwise OR. This makes sense, since one of the
bits denies delaying writes (WT, UC), and the other denies delaying
reads (WC, UC).
-hpa
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