The PCI express spec requires the platform to provide access to this space
for express-compliance. More devices will be using this space as express
becomes the dominant IO bus technology.
>> As far as the device is concerned, after the Northbridge translates
There may have been devices that incorrectly applied the PCI spec to
various fields in the header, I'll grant you that.
However, there is no way a device can determine electrically whether the
Northbridge received Port IO or MMCONFIG cycles. This is between the CPU
and the Northbridge and is utterly opaque to the devices on the bus.
>> The patch I devised concerned itself with Northbridges and separated
Which is why Loic's proposal and Ivan's implementation of it is so elegant.
It solves all these problems in one sweep, and eliminates the code rendered
cruft by Ivan's patch. A two-fer, by my reckoning.
>> In other words, for x86, I don't think we need to worry about Port
The PCI spec provides for conf1 as an architected solution. It's not
going away, and especially not in x86 land where Port IO is built-in
to the CPU.
