Alan Cox wrote:
quoted text
>> bus abort on the LPC bus".   More problematic is that I would think some 
>> people might want to turn on the AMD feature that generates machine 
>> checks if a bus timeout happens.   The whole point of machine checks is 
>>     
>
> An ISA/LPC bus timeout is fulfilled by the bridge so doesn't cause an MCE.
>
>
>   
Good possibility, but the documentation on HyperTransport suggests 
otherwise, even for LPC bridges in this particular modern world of 
AMD64. I might do the experiment someday to see if my LPC bridge is 
implemented in a way that does or doesn't support enabling MCE's. Could 
be different between Intel and AMD - I haven't had reason to pore over 
the Intel chipset specs, since my poking into all this stuff has been 
driven by my personal machine's issues, and it's not got any Intel 
compatible parts.
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