The way C1e works on AMD is that even when one core is woken up
by the PIT the APIC timer resumes on the other core on the socket too because
the deep power saving that breaks the APIC timer is only active
with both cores idle.
And on true multi socket systems there is currently no such deep
C1e -- apic timer should always work.
At least that is how it was supposed to work and while I admit
I haven't read every mail in this endless thread closely I didn't
think Rafael's box contradicted that.
Yes the C1e patch is completely redundant on a non clockevents kernel.
Well, a change is only needed together with clockevent's "apicrunsmaintimer"
default; but not on any non clockevents kernel.
-Andi
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