> The IT8716F accepts commands byte-wise and does all of the lifting onNone that I know of. You might find it's easier to just work with a bastardized version of the (latest, with the 2.6.24 MTD updates so it handleds even more chips) m25p80 driver and not go through the SPI framework. It doesn't look like you could even bitbang SPI there, since not all those pins are usable for bit-level I/O. As you note, that hardware doesn't support all that a SPI controller does. It's provided for accessing a single serial flash chip; and not even to do that very smoothly. You'd have to somehow prevent that driver from reading or writing normal size blocks. And you'd need to defend against drivers trying to do full duplex or multi-segment I/O requests, etc. Lots more work than a bastardized m25p80 driver. ;) My limited exposure to SPI on PC hardware -- LPC chips like this, and newer southbridges -- suggests they tend to be just as, erm, "limited" as this one in terms of supporting anything other than one particular variety of serial flash interface. I think the idea was just to let board makers use cheaper flash chips when loading the BIOS. For that, they don't need the kind of flexible expansion bus SPI is on most SOC chips; or much throughput. - Dave -
| Ingo Molnar | [patch 12/13] syslets: x86: optimized copy_uatom() |
| Greg Kroah-Hartman | [PATCH 017/196] aoechr: Convert from class_device to device |
| Yinghai Lu | Re: 2.6.26, PAT and AMD family 6 |
| Jan Engelhardt | intel iommu (Re: -mm merge plans for 2.6.23) |
git: | |
| Gerrit Renker | [PATCH 27/37] dccp: Integration of dynamic feature activation - part 2 (server side) |
| David Miller | [GIT]: Networking |
| David Miller | Re: [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
| Natalie Protasevich | [BUG] New Kernel Bugs |
