On Tuesday, September 25, 2007 11:49:50 pm Grant Grundler wrote:
quoted text
> Upon reading the "2) Platforms that permit DMA reordering", I think I
> have been confusing coherency with ordering. I think I have because DMA
> is leaving the "PCI domain", crossing an "unordered domain" (NUMA,
> interconnect), and then finally hitting the cache coherency "domain"
> when it reaches a "far away" memory controller. That's why I've
> been thinking of this as a coherency problem.
>
> The description and API uses the word "flush" (which is ok I guess) instead
> of describing this in terms of enforcing DMA ordering.  Any DMA write to
> the "strongly ordered" region will cause _all_ inflight DMA to be visible
> to cache coherency, thus preserving the illusion of strong DMA ordering.
>
> Does that sound right/better to you too?
> I don't have chipset docs and some of this is just trying to rephrase
> what I've heard before from former SGI employees.

I definitely wouldn't describe this as a coherency issue--the lines involved 
in the DMA writes are fully coherent.  It's really an ordering problem, and 
the new API is setting a "barrier" bit in the DMA address that indicates to 
the bridge that any outstanding DMA should be written before the barriered 
data.  So calling it set_flush or set_barrier is fine with me...

Jesse
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