Hi,
I'll attach 4 patches for Intel FB (i830+) here:
1/4 - whitespace, bracket and other clean-ups (rather long)

      working with kernel-style brackets instead of:

----------------

void

function_name (int arg) {

----------------

      is a bit easier. I think it would be best to apply it in the

      beginning of the "patch period" to avoid potential conflicts.
2/4 - obvious changes and corrections
3/4 - the chip adds two halflines automatically in interlaced mode,

      we have to force the number of lines to be even
4/4 - allow odd- and even-field-first in interlaced modes, and

      proper sync to vertical retrace. It enables video players

      (got it working with MPlayer currently) to play perfect

      field-synced stream to RGB-connected (VGA output) TV set.
      This patch adds #define FB_VMODE_ODD_FLD_FIRST 4 in

      include/linux/fb.h, to be able to force odd field first (analog

      broadcast PAL and some PAL DVD discs use it) instead of even

      field (bottom) first, as used by NTSC, DV PAL, some PAL

      DVDs etc. Interlaced-only thing.
      This change need a coresponding change in fbset and probably in

      media players which want to set video mode themselves, I will

      do the fbset part and maybe MPlayer's if the fb.h patch is ok.
All four patches change only files in drivers/video/intelfb/, except

patch 4/4 which also adds FB_VMODE_ODD_FLD_FIRST in include/linux/fb.h.
Tested on i915G in 1440x576 50 Hz (I) with PAL TV.

--

Krzysztof Halasa

-

Intel FB: allow odd- and even-field-first in interlaced modes, and

proper sync to vertical retrace
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
--- a/drivers/video/intelfb/intelfbhw.c

+++ b/drivers/video/intelfb/intelfbhw.c

@@ -376,7 +376,7 @@ int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 	dinfo->vsync.pan_offset = offset;

 	if ((var->activate & FB_ACTIVATE_VBL) &&

-	    !intelfbhw_enable_irq(dinfo, 0))

+	    !intelfbhw_enable_irq(dinfo))

 		dinfo->vsync.pan_display = 1;

 	else {

 		dinfo->vsync.pan_display = 0;

@@ -1240,7 +1240,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,

 	u32 tmp;

 	const u32 *dpll, *fp0, *fp1, *pipe_conf;

 	const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;

-	u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;

+	u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;

 	u32 hsync_reg, htotal_reg, hblank_reg;

 	u32 vsync_reg, vtotal_reg, vblank_reg;

 	u32 src_size_reg;

@@ -1281,6 +1281,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,

 		fp0_reg = FPB0;

 		fp1_reg = FPB1;

 		pipe_conf_reg = PIPEBCONF;

+		pipe_stat_reg = PIPEBSTAT;

 		hsync_reg = HSYNC_B;

 		htotal_reg = HTOTAL_B;

 		hblank_reg = HBLANK_B;

@@ -1304,6 +1305,7 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,

 		fp0_reg = FPA0;

 		fp1_reg = FPA1;

 		pipe_conf_reg = PIPEACONF;

+		pipe_stat_reg = PIPEASTAT;

 		hsync_reg = HSYNC_A;

 		htotal_reg = HTOTAL_A;

 		hblank_reg = HBLANK_A;

@@ -1390,6 +1392,17 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,

 	OUTREG(vtotal_reg, *vt);

 	OUTREG(src_size_reg, *ss);
+	switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |

+					  FB_VMODE_ODD_FLD_FIRST)) {

+	case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:

+		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);

+		break;

+	case FB_VMODE_INTERLACED: /* even lines first */

+		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);

+		break;

+	default:		/* non-interlac...
[ message continues ]

Intel FB: the chip adds two halflines automatically in interlaced mode,

force even line count for the right timings.
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
--- a/drivers/video/intelfb/intelfbhw.c

+++ b/drivers/video/intelfb/intelfbhw.c

@@ -317,6 +317,14 @@ int intelfbhw_validate_mode(struct intelfb_info *dinfo,

 			var->yres, VACTIVE_MASK + 1);

 		return 1;

 	}

+	if (var->xres < 4) {

+		WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);

+		return 1;

+	}

+	if (var->yres < 4) {

+		WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);

+		return 1;

+	}
 	/* Check for doublescan modes. */

 	if (var->vmode & FB_VMODE_DOUBLE) {

@@ -324,6 +332,11 @@ int intelfbhw_validate_mode(struct intelfb_info *dinfo,

 		return 1;

 	}
+	if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {

+		WRN_MSG("Odd number of lines in interlaced mode\n");

+		return 1;

+	}

+

 	/* Check if clock is OK. */

 	tmp = 1000000000 / var->pixclock;

 	if (tmp < MIN_CLOCK) {

@@ -1127,6 +1140,8 @@ int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,

 		hblank_end);
 	vactive = var->yres;

+	if (var->vmode & FB_VMODE_INTERLACED)

+		vactive--; /* the chip adds 2 halflines automatically */

 	vsync_start = vactive + var->lower_margin;

 	vsync_end = vsync_start + var->vsync_len;

 	vtotal = vsync_end + var->upper_margin;

-

Intel FB: obvious changes and corrections
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
--- a/drivers/video/intelfb/intelfb.h

+++ b/drivers/video/intelfb/intelfb.h

@@ -355,7 +355,10 @@ struct intelfb_info {

 	struct intelfb_output_rec output[MAX_OUTPUTS];

 };
-#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))

+#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) ||	\

+			((dinfo)->chipset == INTEL_915GM) ||	\

+			((dinfo)->chipset == INTEL_945G) ||	\

+			((dinfo)->chipset==INTEL_945GM))
 #ifndef FBIO_WAITFORVSYNC

 #define FBIO_WAITFORVSYNC	_IOW('F', 0x20, __u32)

--- a/drivers/video/intelfb/intelfbhw.c

+++ b/drivers/video/intelfb/intelfbhw.c

@@ -434,14 +434,14 @@ void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,

 			 unsigned red, unsigned green, unsigned blue,

 			 unsigned transp)

 {

+	u32 palette_reg = (dinfo->pipe == PIPE_A) ?

+			  PALETTE_A : PALETTE_B;

+

 #if VERBOSE > 0

 	DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",

 		regno, red, green, blue);

 #endif
-	u32 palette_reg = (dinfo->pipe == PIPE_A) ?

-			  PALETTE_A : PALETTE_B;

-

 	OUTREG(palette_reg + (regno << 2),

 	       (red << PALETTE_8_RED_SHIFT) |

 	       (green << PALETTE_8_GREEN_SHIFT) |

@@ -1305,8 +1305,8 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
 	count = 0;

 	do {

-		tmp_val[count%3] = INREG(0x70000);

-		if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))

+		tmp_val[count % 3] = INREG(PIPEA_DSL);

+		if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))

 			break;

 		count++;

 		udelay(1);

@@ -2004,7 +2004,6 @@ intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
 void

 intelfbhw_disable_irq(struct intelfb_info *dinfo) {

-	u16 tmp;
 	if (test_and_clear_bit(0, &dinfo->irq_flags)) {

 		if (dinfo->vsync.pan_display) {

@...
[ message continues ]

Intel FB: whitespace, bracket and other clean-ups
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
--- a/drivers/video/intelfb/intelfb.h

+++ b/drivers/video/intelfb/intelfb.h

@@ -231,8 +231,8 @@ struct intelfb_hwstate {

 struct intelfb_heap_data {

 	u32 physical;

 	u8 __iomem *virtual;

-	u32 offset;  // in GATT pages

-	u32 size;    // in bytes

+	u32 offset;		/* in GATT pages */

+	u32 size;		/* in bytes */

 };
 #ifdef CONFIG_FB_INTEL_I2C

@@ -270,9 +270,9 @@ struct intelfb_info {

 	struct intelfb_hwstate save_state;
 	/* agpgart structs */

-	struct agp_memory *gtt_fb_mem;     // use all stolen memory or vram

-	struct agp_memory *gtt_ring_mem;   // ring buffer

-	struct agp_memory *gtt_cursor_mem; // hw cursor

+	struct agp_memory *gtt_fb_mem;     /* use all stolen memory or vram */

+	struct agp_memory *gtt_ring_mem;   /* ring buffer */

+	struct agp_memory *gtt_cursor_mem; /* hw cursor */
 	/* use a gart reserved fb mem */

 	u8 fbmem_gart;

@@ -346,7 +346,7 @@ struct intelfb_info {
 	/* driver registered */

 	int registered;

-

+

 	/* index into plls */

 	int pll_index;
--- a/drivers/video/intelfb/intelfb_i2c.c

+++ b/drivers/video/intelfb/intelfb_i2c.c

@@ -58,7 +58,8 @@ static void intelfb_gpio_setscl(void *data, int state)

 	struct intelfb_info *dinfo = chan->dinfo;

 	u32 val;
-	OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) | SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);

+	OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) |

+	       SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);

 	val = INREG(chan->reg);

 }
@@ -68,7 +69,8 @@ static void intelfb_gpio_setsda(void *data, int state)

 	struct intelfb_info *dinfo = chan->dinfo;

 	u32 val;
-	OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) | SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);

+	OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) |

+	       SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);

 	val = INREG(chan->reg);

 }
@@ -97,26 +99,26 @@ static int intelfb_gpio_getsda(void *data)

 }
 static int intelf...
[ message continues ]