This is the driver for latest Blackfin on-chip nand flash controller

 - use nand_chip and mtd_info common nand driver interface
 - provide both PIO and dma operation
 - compiled with ezkit bf548 configuration
 - use hardware 1-bit ECC
 - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs

ChangeLog from try#1
 - use hweight32() instead of count_bits()
 - replace bf54x with bf5xx and BF54X with BF5XX
 - compare against plat->page_size in 2 cases when enable hardware ECC

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
---
 drivers/mtd/nand/Kconfig              |   19 +
 drivers/mtd/nand/Makefile             |    1 +
 drivers/mtd/nand/bf5xx_nand.c         |  791 +++++++++++++++++++++++++++++++++
 include/asm-blackfin/mach-bf548/dma.h |    1 +
 include/asm-blackfin/nand.h           |   47 ++
 5 files changed, 859 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bf5xx_nand.c
 create mode 100644 include/asm-blackfin/nand.h

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7992c43..3c88bb8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -131,6 +131,25 @@ config MTD_NAND_AU1550
 	  This enables the driver for the NAND flash controller on the
 	  AMD/Alchemy 1550 SOC.
 
+config MTD_NAND_BF5XX
+	tristate "Blackfin on-chip NAND Flash Controller driver"
+	depends on BF54x && MTD_NAND
+	help
+	  This enables the Blackfin on-chip NAND flash controller
+
+	  No board specific support is done by this driver, each board
+	  must advertise a platform_device for the driver to attach.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called bf5xx-nand.
+
+config MTD_NAND_BF5XX_HWECC
+	bool "BF5XX NAND Hardware ECC"
+	depends on MTD_NAND_BF5XX
+	help
+	  Enable the use of the BF5XX's internal ECC generator when
+	  using NAND.
+
 config MTD_NAND_RTC_FROM4
 	tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)"
 	depends on SH_SOLUTION_ENGINE
diff --gi...
[ message continues ]

This is the driver for latest Blackfin on-chip nand flash controller

 - use nand_chip and mtd_info common nand driver interface 
 - provide both PIO and dma operation 
 - compiled with ezkit bf548 configuration 
 - use hardware 1-bit ECC 
 - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs

ChangeLog from try#1 
 - use hweight32() instead of count_bits() 
 - replace bf54x with bf5xx and BF54X with BF5XX 
 - compare against plat->page_size in 2 cases when enable hardware ECC

ChangeLog from try#2
 - passed nand_test suites
 - use cpu_relax() instead of busy wait loop
 - some coding style issue pointed out by Andrew

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
---
 drivers/mtd/nand/Kconfig              |   19 +
 drivers/mtd/nand/Makefile             |    1 +
 drivers/mtd/nand/bf5xx_nand.c         |  788 +++++++++++++++++++++++++++++++++
 include/asm-blackfin/mach-bf548/dma.h |    1 +
 include/asm-blackfin/nand.h           |   47 ++
 5 files changed, 856 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bf5xx_nand.c
 create mode 100644 include/asm-blackfin/nand.h

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7992c43..3c88bb8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -131,6 +131,25 @@ config MTD_NAND_AU1550
 	  This enables the driver for the NAND flash controller on the
 	  AMD/Alchemy 1550 SOC.
 
+config MTD_NAND_BF5XX
+	tristate "Blackfin on-chip NAND Flash Controller driver"
+	depends on BF54x && MTD_NAND
+	help
+	  This enables the Blackfin on-chip NAND flash controller
+
+	  No board specific support is done by this driver, each board
+	  must advertise a platform_device for the driver to attach.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called bf5xx-nand.
+
+config MTD_NAND_BF5XX_HWECC
+	bool "BF5XX NAND Hardware ECC"
+	depends on MTD_NAND_BF5XX
+	help
+	  Enable the use of the BF5XX's internal ECC generator when
+	  ...
[ message continues ]

Bryan,

I'd suggest you to test your NAND driver with the following NAND tests:

git://git.infradead.org/~ahunter/nand-tests.git

(http://git.infradead.org/?p=users/ahunter/nand-tests.git;a=summary)


You may want to avoid the torture test, but it is useful to run it with
limited amount of erase cycles to make sure your flash/driver survives
really high I/O load.For example, we caught occasional DMA transfer
problems while running the torture test for few days.

-- 
Best regards,
Artem Bityutskiy (Битюцкий Артём)

-

Thanks Artem, I got the code and did some test on my EZKIT548 with this
driver.

Here is the test log, only 2 errors in oobtest. After digging into the
mtd-nand driver code, it should be no relation to my bf5xx_nand driver.
Maybe somethings wrong in the mtd-nand code. I intend to get some help
from you, please see my test log below:

1. boot message:
---
Linux version 2.6.22.6-ADI-2007R2-pre-svn3643 (roc@roc-desktop) (gcc
version 4.1.2 (ADI svn)) #38 Mon Sep 10 17:35:51 CST 2007
Hardware Trace Active and Enabled
Blackfin support (C) 2004-2007 Analog Devices, Inc.
Compiled for ADSP-BF549 Rev 0.0
Blackfin Linux support by http://blackfin.uclinux.org/
Processor Speed: 525 MHz core clock and 131 Mhz System Clock
Board Memory: 64MB
Kernel Managed Memory: 64MB
Memory map:
  text      = 0x00001000-0x00117820
  rodata    = 0x00118000-0x001630dc
  data      = 0x00164000-0x00178000
    stack   = 0x00164000-0x00166000
  init      = 0x00178000-0x002c4c4d
  bss       = 0x002c4c50-0x002d4890
  available = 0x002d4890-0x03eff000
  DMA Zone  = 0x03f00000-0x04000000
Instruction Cache Enabled
Data Cache Enabled (write-through)
Built 1 zonelists.  Total pages: 16002
Kernel command line: root=/dev/mtdblock0 rw
ip=192.168.0.66:192.168.0.55:192.168.0.1:255.255.255.0:BF548:eth0:off
Configuring Blackfin Priority Driven Interrupts
PID hash table entries: 256 (order: 8, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Physical pages: 3eff
Memory available: 60968k/64112k RAM, (1331k init code, 1114k kernel
code, 63k data, 1024k dma)
Blackfin Scratchpad data SRAM: 4 KB
Blackfin Data A SRAM: 16 KB (15 KB free)
Blackfin Data B SRAM: 16 KB (16 KB free)
Blackfin Instruction SRAM: 48 KB (42 KB free)
Security Framework v1.0.0 initialized
Capability LSM initialized
Mount-cache hash table entries: 512
NET: Registered protocol family 16
Blackfin GPIO Controller
Blackfin DMA Controller
stamp_init(): registering devi...
[ message continues ]

Hi,


This means that MTD did not return an error when the test tried to read
the last NAND page's OOB. Here is the code:

/* Attempt to write off end of device */
ops.mode      = MTD_OOB_AUTO;
ops.ooblen    = mtd->ecclayout->oobavail + 1;
ops.oobbuf    = writebuf;
printk(PRINT_PREF "Attempting to write past end of device\n");
printk(PRINT_PREF "An error is expected...\n");
err = mtd->write_oob(mtd, mtd->size - mtd->writesize, &ops);

So we read OOB size + 1 byte from the last NAND page and get no error.

This test passes for nandsim, so I'm not sure the problem is in the
generic code. On the other hand, it is generic code which should check


We are planning to clean up the tests and submit them for kernel
inclusion some day, when we have time.

-- 
Best regards,
Artem Bityutskiy (Битюцкий Артём)

-

Actually, I debugged both oobtest.c and drivers/mtd/nand/nand_base.c

in the kernel nand_base.c
mtd->read_oob() --> nand_read_oob() --> nand_do_read_oob() -->
chip->ecc.read_oob() --> nand_read_oob_std() --> chip->read_buf() -->
bf5xx_nand.c bf5xx_nand_dma_read_buf().

In the calling path, rage check should not be in my driver code
bf5xx_nand_dma_read_buf() like other low level nand controller drivers.
It is already in nand_do_read_oob() as below:

---
	/* Do not allow reads past end of device */
	if (unlikely(from >= mtd->size ||
		     ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
					(from >> chip->page_shift)) * len)) {
		DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
			"Attempt read beyond end of device\n");
		return -EINVAL;
	}
---

maybe this condition testing does not include your case. I am not sure,

Good news. Thanks
Best Regards,
- Bryan Wu

-