http://bugzilla.kernel.org/show_bug.cgi?id=8833
We write 0xffffffff to BARs to detect BAR size, this will change BAR
base to 0xfxxxxxx depends on BAR size. In the bug, PCI MCFG base address
is 0xf4000000. One PCI device (gfx) has a 256M BAR, the detection code
will temprarily change it to 0xf0000000, so conflict with MCFG decode
range. Later memory based config space read/write address is decoded by
both MCH and gfx and cause a hang. This patch disables resource decode
in BAR size detection to avoid resource conflict.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
---
drivers/pci/probe.c | 6 ++++++
1 file changed, 6 insertions(+)
Index: linux/drivers/pci/probe.c
===================================================================
--- linux.orig/drivers/pci/probe.c 2007-09-12 10:44:19.000000000 +0800
+++ linux/drivers/pci/probe.c 2007-09-13 12:58:18.000000000 +0800
@@ -185,6 +185,11 @@ static void pci_read_bases(struct pci_de
unsigned int pos, reg, next;
u32 l, sz;
struct resource *res;
+ u16 command;
+
+ pci_read_config_word(dev, PCI_COMMAND, &command);
+ pci_write_config_word(dev, PCI_COMMAND,
+ command & (~(PCI_COMMAND_MEMORY|PCI_COMMAND_IO)));
for(pos=0; pos<howmany; pos = next) {
u64 l64;
@@ -283,6 +288,7 @@ static void pci_read_bases(struct pci_de
}
}
}
+ pci_write_config_word(dev, PCI_COMMAND, command);
}
void pci_read_bridge_bases(struct pci_bus *child)
-
