On Monday 06 August 2007, Rafael J. Wysocki wrote:
quoted text
> Section 5.4.1 of PCI PM 1.1. spec is about D3_hot.  Specifically, it says
> that if a device in D3_hot is programmed to D0, it performs the equivalent of
> a warm reset.  IOW, this is supposed to happen if the current state is D3_hot
> and the targed state is D0, which is covered by the code snippet above.

Actually, it's *allowed* to do a warm reset.  Not required.
And not all PCI devices will do such a reset.   Some of them
will return to D0_initialized ... not D0_uninitialized (where
uninitialized means "did the reset").

It's D3_cold where a (powerup) reset is *required*.

A common example would be a USB host controller.  If one of
those did a warm reset it'd trash all the connection state
which was carefully retained during sleep ... and there'd be
no point to supporting D3_hot rather than D3_cold.

As a rule of thumb, it's probably safe to assume that if
a device can generate wakeup events, it probably doesn't
trash all of its state when it resumes from D3_hot.

Of course, if it can generate wakeup events from D3_cold,
the difference between Vaux and Vcc power wells comes into
play.  The Vaux powered bits will retain state, while the
stuff powered by Vcc gets a powerup reset.

If it can't generate wakeup events, a PCI device has no
particular need to retain state after D3.  Implementors
can choose whichever is most convenient.

- Dave
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