On Monday, 6 August 2007 17:50, Joonwoo Park wrote:
quoted text
> 2007/8/6, Rafael J. Wysocki <rjw@sisk.pl>:
> > On Monday, 6 August 2007 15:42, Joonwoo Park wrote:
> > > Hi.
> > > I think that the pci_set_power_state() has bug.
> > > The specification says that some delays is required.
> >
> > And they are in place, AFAICS (from drivers/pci/pci.c):
> >
> >        /* Mandatory power management transition delays */
> >        /* see PCI PM 1.1 5.6.1 table 18 */
> >        if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
> >                msleep(pci_pm_d3_delay);
> >        else if (state == PCI_D2 || dev->current_state == PCI_D2)
> >                udelay(200);
> >
> 
> The problem is occurred when state is 'PCI_D0', so those codes can't cover it.
> But pci pm specification 5.4.1 says that when programmed to D0 the
> equivalent of a warm reset, delay for the duration of the D3hot to D0
> Uninitialized state
> transition (10ms) to pci signal drivers remain disabled is required.

Section 5.4.1 of PCI PM 1.1. spec is about D3_hot.  Specifically, it says
that if a device in D3_hot is programmed to D0, it performs the equivalent of
a warm reset.  IOW, this is supposed to happen if the current state is D3_hot
and the targed state is D0, which is covered by the code snippet above.

Greetings,
Rafael


-- 
"Premature optimization is the root of all evil." - Donald Knuth
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