On Tue, Aug 21, 2007 at 08:14:09PM -0500, James Bottomley wrote:
quoted text
> On Tue, 2007-08-21 at 17:34 -0700, akepner@sgi.com wrote:
> .....
> > On Altix, DMA from a device isn't guaranteed to arrive in host memory 
> > in the order it was sent from the device. This reordering can happen 
> > in the NUMA interconnect (it's specifically not a PCI reordering.)
> 
> This is mmiowb and read_relaxed() again, isn't it?
> .....

No, this is different. 

This problem here has do with ordering writes from the device 
to host memory. Specifically this problem can be manifested with 
Infiniband - when a Completion Queue Entry is written by the IB 
device, it indicates that data is available in host memory. But 
the write to the Completion Queue can race with DMA of data. 

(Completion Queues can be allocated by the kernel or in userspace. 
The race described above can only happen when they are allocated 
in userspace - kernel allocations of CQs use dma_alloc_coherent() 
and so get the "barrier" attribute that's needed to prevent the 
race. The proposed new interface would allow CQs, or anything else, 
allocated with plain old malloc(), to set the barrier attribute.)

-- 
Arthur

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