On Wed, Aug 15, 2007 at 06:41:40PM -0700, Christoph Lameter wrote:
There are indeed architectures where you can cause gcc to emit memory
barriers in response to volatile. I am assuming that we are -not-
making gcc do this. Given this, then volatiles and memory barrier
instructions are orthogonal -- one controls the compiler, the other
controls the CPU.
Thanx, Paul
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