On Fri, Jul 06, 2007 at 10:50:30AM -0700, Li, Tong N wrote:
^^^^^^^
I meant L2 cache hit of course
I found that memory latency is difficult to measure in modern x86
CPUs because they have very clever prefetchers that can often
outwit benchmarks.
Another trap on P4 is that RDTSC is actually quite slow and synchronizes
the CPU; that can add large measurement errors.
-Andi
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